UPD16449N NEC [NEC], UPD16449N Datasheet - Page 18

• Manufacturer Part Number: UPD16449N
• Description: SOURCE DRIVER FOR 240-OUTPUT TFT-LCD
• Manufacturer: NEC [NEC]

Cautions 1. Turn on power to V
18
2.
3.
4.
5.
6.
7.
SHP
SHP
SHP
STHR (STHL)
destruction due to latch-up, and turn off power in the reverse sequence. Observe this power
sequence even during the transition period.
The PD16449 is designed to input successive signals such as chrome signals. The input band
of the video signals is designed to be 9 MHz MAX. If video signals faster than that are input,
display is not performed correctly.
Insert a bypass capacitor of 0.1 F between V
power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage
fluctuates.
Display may not be correctly performed if noise is superimposed on the start pulse pin.
Therefore, be sure to input a reset signal during the vertical blanking period.
Even if the start pulse width is extended by half a clock or more, sampling start timing SHP
not affected, and the sampling operation is performed normally.
When the multiplexer circuit is used in the vertical stripe mode, C1 to C3 are simultaneously
sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a
shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L".
When using the multiplexer circuit in the delta array mode or mosaic array mode, C1 to C3 are
sequentially sampled. Input a three-phase clock to CLI1 through CLI3 (for the sampling timing,
refer to 5. FUNCTIONAL DESCRIPTION.).
The recommended timing of t
chart shows simultaneous sampling.).
pulse is input after reset, sampling is not performed in the correct sequence.
An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH
4
1
7
to SHP
to SHP
to SHP
RESET
CLI1
INH
6
3
9
t
ISETUP
t
R–I
PW
DD1
RES
, logic input, V
1
PW
R-1
Data Sheet S15677EJ1V0DS
INH
2
and PW
: 5 clocks MIN.
DD2
t
3
IHOLD
, and video signal input in that order to prevent
RES
4
on starting is shown below (The following timing
5
DD1
and V
3 clocks MIN.
1
SS1
and between V
2
3
DD2
and V
SS2
. If the
PD16449
1
is