ov9650 OmniVision Technologies, Inc, ov9650 Datasheet - Page 14

• Manufacturer Part Number: ov9650
• Description: Color Cmos Sxga 1.3 Megapixel Camerachiptm With Omnipixel
• Manufacturer: OmniVision Technologies, Inc

14
Table 5
Address
(Hex)
0F
10
12
13
11
Proprietary to OmniVision Technologies
Register
Device Control Register List (Continued)
CLKRC
COM6
COM7
COM8
Name
AECH
Default
(Hex)
43
40
00
00
8F
R/W
RW
RW
RW
RW
RW
Common Control 6
Exposure Value
Data Format and Internal Clock
Common Control 7
Common Control 8
Bit[7]:
Bit[6:4]: Reserved
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
Bit[7:0]: AEC[9:2] (see registers
Bit[7]:
Bit[6]:
Bit[5:0]: Internal clock pre-scalar
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4:3]: Reserved
Bit[2]:
Bit[1]:
Bit[0]:
Output of optical black line option
0:
1:
Enable bias for ADBLC
ADBLC offset
0:
1:
Reset all timing when format changes
Enable ADBLC option
for AEC[1:0])
Digital PLL option
0:
1:
Use input clock directly (no clock pre-scale available)
F(internal clock) = F(input clock)/(Bit[5:0]+1)
•
SCCB Register Reset
0:
1:
Output format - VGA selection
Output format - CIF selection
Output format - QVGA selection
Output format - QCIF selection
Output format - RGB selection
Reserved
Output format - Raw RGB (COM7[2] must be set high)
Enable fast AGC/AEC algorithm
AEC - Step size limit
0:
1:
Banding filter ON/OFF
AGC Enable
AWB Enable
AEC Enable
Disable HREF at optical black
Enable HREF at optical black
Use 4-channel ADBLC
Use 2-channel ADBLC
Disable double clock option, meaning the maximum
PCLK can be as high as half input clock
Enable double clock option, meaning the maximum
PCLK can be as high as input clock
Range: [0 0000] to [1 1111]
No change
Resets all registers to default values
Fast condition change maximum step is VSYNC
Unlimited step size
AMERA
Description
HIP
AECHM
Version 1.91, January 28, 2005
for AEC[15:10] and
O
mni
COM1
ision