UPD16782P NEC [NEC], UPD16782P Datasheet
UPD16782P
Related parts for UPD16782P
UPD16782P Summary of contents
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SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV) DESCRIPTION PD16782 is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and ...
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BLOCK DIAGRAM STHR R,/L CLI1~CLI3 INH Osel C RESET C1 C2 Multiplexer C3 MP/TH MP/1.5 2. SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT Video Line 2 300-bit bidirectional shift register Level shifter Sample and ...
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PIN CONFIGURATION Input dummy pin RMON1 RMON1 Connected resistance measurement pin V DD2 V SS1 V DD1 STHL MP/TH MP/1.5 R,/L RESET INH CLI1 CLI2 CLI3 TEST STHR Osel V DD1 V SS1 V DD2 Connected ...
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No. PAD Name Dummy1 -464.0 8451.0 2 RMON1 -464.0 8014.2 3 RMON1 -464.0 7842 -464.0 7538.6 DD2 5 V -464.0 7458.6 DD2 6 V -464.0 7378.6 DD2 7 V -464.0 7298.6 ...
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No. PAD Name Bump Size (X: 111 V -464.0 -7218.6 DD2 112 V -464.0 -7298.6 DD2 113 V -464.0 -7378.6 DD2 114 V -464.0 -7458.6 DD2 115 V -464.0 -7538.6 DD2 116 ...
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No. PAD Name 221 S 402.0 -3398.5 92 222 S 402.0 -3341.5 93 223 S 402.0 -3284.5 94 224 S 402.0 -3227.5 95 225 S 402.0 -3170.5 96 226 S 402.0 -3113.5 97 227 ...
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No. PAD Name Bump Size (X: 331 S 402.0 2871.5 202 332 S 402.0 2928.5 203 333 S 402.0 2985.5 204 334 S 402.0 3042.5 205 335 S 402.0 3099.5 206 336 ...
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PIN FUNCTIONS Symbol Pin Name Pad No Video signal input Video signal output 130 to 429 1 300 STHR, Cascade I 86, STHL CLI1 to ...
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FUNCTIONAL DESCRIPTION 5.1 Multiplexer Circuit This circuit selects RGB video signals input to the pins according to the pixel array of the liquid crystal panel, and outputs the signals to the S through S 1 Vertical ...
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Figure 5 2. Timing Chart of Vertical Stripe Array RESET INH 300 Sampling C1 (C3) undifined input data Output undifined 299 C2 (C2) Sampling undifined input data Output undifined ...
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Single-side delta array mode (MP/ MP/1 Table 5 2. Relation between Video Signals C1 to C3, and Output Pins Line No. (number RESET INH of INHs ...
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Figure 5 4. Timing Chart of Single-Side Delta Array RESET INH 300 Sampling undifined undifined input data Output undifined 299 undifined Sampling undifined input data Output undifined 298 ...
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Double-side delta array mode (MP/ MP/1 Table 5 3. Relation between Video Signals and Output Pins Line No. (number RESET INH of INHs ...
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Figure 5 6. Timing Chart of Both-Sides Delta Array RESET INH 300 Sampling undifined undifined input data Output undifined 299 undifined Sampling undifined input data Output undifined 298 ...
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Mosaic array mode (MP/ MP/1 Table 5 4. Relation between Video Signals C1 to C3, and Output Pins Line No. (number RESET INH of INHs ...
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Figure 5 8. Timing Chart of Mosaic Array RESET INH 300 Sampling undifined undifined input data Output undifined 299 undifined Sampling undifined input data Output undifined 298 undifined ...
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Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling ( ( ) indicates the case of left shift.) CLI1 STHR (STHL) SHP (SHP ) 1 300 SHP (SHP ) 2 299 SHP (SHP ) 3 ...
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Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and ...
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Cautions 1. Turn on power logic input, V DD1 due to latch-up, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. The PD16782 is designed to input successive ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Logic supply voltage V DD1 Driver supply voltage V DD2 Logic input voltage V I Video input voltage V VI Logic output voltage V 01 Driver ...
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Electrical Characteristics ( + Parameter Symbol Maximum video signal output voltage V VOH Minimum video signal output voltage V VOL Logic high level output voltage V LOH Logic low level output voltage V LOL ...
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Switching Characteristics ( + Parameter Symbol Start pulse propagation delay t PHL time t PLH Clock frequency 1 f CLK 1 Clock frequency 2 f CLK 2 Logic input capacitance C I1 STHL, STHR ...
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Switching Characteristic Waveform (Simultaneous/successive sampling) Start Pulse Input Timing PW 1 CLI 50% CLI1 t SETUP STHR 50% (STHL) SHP 1 (SHP ) 300 Start Pulse Output Timing 50% CLI1 t PLH STHL (STHR) Remark The input/output timing of the ...
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RESET INH Pulse Timing CLI1 PW RES 50% RESET INH 24 50% 50 IIHOLD ISETUP 50 INH R-I Data Sheet S15806EJ1V0DS PD16782 50% ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to ...