edd51323dbh-ls Elpida Memory, Inc., edd51323dbh-ls Datasheet - Page 35
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edd51323dbh-ls
Manufacturer Part Number
edd51323dbh-ls
Description
512m Bits Ddr Mobile Ram
Manufacturer
Elpida Memory, Inc.
Datasheet
1.EDD51323DBH-LS.pdf
(59 pages)
- Current page: 35 of 59
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A Write Command to the Consecutive Read Command Interval: To Complete the Burst Operation
1. Same
2. Same
3. Different
Preliminary Data Sheet E1432E11 (Ver. 1.1)
Command
Destination row of the consecutive read
command
Bank
address
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
DQS
/CK
DM
DQ
CK
WRIT
Row address State
Same
Different
Any
t0
in0
t1
ACTIVE
—
ACTIVE
IDLE
in1
INPUT
tWRD (min)
NOP
WRITE to READ Command Interval
in2
t2
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
in3
t3
tWTR*
35
READ
tn
tn + 1
EDD51323DBH-LS
NOP
tn + 2
out0
OUTPUT
tn + 3
out1
BL = 4
CL = 3
out2
tn + 4
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