PLL202-03 PhaseLink (PLL), PLL202-03 Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
PLL202-03
Manufacturer Part Number
PLL202-03
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., SST
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL202-03.pdf
(13 pages)
8. BYTE 7: Linear Programming Register (1=Enable, 0=Disable)
9. BYTE 8: Device ID Register (1=Enable, 0=Disable)
Note: *: Default value at power-up
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Motherboard Clock Generator for SIS540/630 with 133MHz FSB
Pin#
Pin#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Linear programming sign bit ( 0 is “ ”, 1 is “ ” )
Linear programming magnitude bit 6 (MSB)
Linear programming magnitude bit 5
Linear programming magnitude bit 4
Linear programming magnitude bit 3
Linear programming magnitude bit 2
Linear programming magnitude bit 1
Linear programming magnitude bit 0 (LSB)
Reserved
Device ID Bit 6*
Device ID Bit 5*
Device ID Bit 4*
Device ID Bit 3*
Device ID Bit 2*
Device ID Bit 1*
Device ID Bit 0*
Description
Description
PLL202-03
Rev 02/15/00 Page 8