PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet
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PLL202-108
Related parts for PLL202-108
PLL202-108 Summary of contents
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... VDDHTT • HTTT (0:1) HTTC (0:1) KEY SPECIFICATIONS VDD AGP (0:1) • PCI (0:8) • PCIF VDD • 48Mhz • • 24_48Mhz • • WDRESET# • • • • PLL202-108 1 48 VDDREF 2 47 XIN 3 46 XOUT 4 45 VSSREF 5 44 REF0/FS2 REF1/FS0 PCI8//PCISTOP#^ ...
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... Differential pair output for CPU Chip Sets. B This pin latches the MODE value at power-up. After power-up, this pin acts as 24_48MHz clock output with default 24MHz or selection by I2C. MODE function is to select mobile or desktop mode for pin 7. It has 120K ohm internal pull up resistor. PLL202-108 Description Rev 8/20/02 Page 2 ...
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... PLL. P 3.3v power supply for CPU[T,C]_[0:1] clocks. P 3.3v power supply for REF[0:2] clocks P Ground. Reference R (Rr VDD/(3*Rr) ref Rr = 221Ω; 1% 50Ω Iref = 5.0mA Rr = 475Ω; 1% 50Ω Iref = 2.32 mA PLL202-108 Description Output Current 6*IREF 1.0V @ 50Ω 7*IREF 0.7V @ 50Ω oh Rev 8/20/02 Page 3 ...
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... PLL202-108 SST α VCO Amplitude (CPU) -0.5% down 400 0.45 -0.5% down 400 0.60 -0.5% down 400 0.90 -0.5% down 333 0.90 ±0.3% center 400 0.30 ±0.3% center 360 0.45 ±0.3% center 420 0.45 ±0.3% center 330 0.90 ±0.3% center 404 0.45 ±0.3% center 404 0.60 ± ...
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... Address Byte count Address Data Byte M Address Data Byte M Byte M+1 P Stop PLL202-108 Data Data A A -------- Byte N Data Data A A -------- Byte M+N-1 Data Data Data A A Byte 1 Byte 2 -------- Data Data ...
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... CPU_STOP# setting for CPU[C/T]_1 (0=Free Running, 1=Stopped) 1 CPU_STOP# setting for AGP0 (0=Free Running, 1=Stopped) 1 CPU_STOP# setting for AGP1 (0=Free Running, 1=Stopped) 1 CPU_STOP# setting for HTT[C/T]_0 (0=Free Running, 1=Stopped) 1 CPU_STOP# setting for HTT[C/T]_1 (0=Free Running, 1=Stopped) 1 CPU[C/T]_0 (1=Active 0=Inactive) 1 CPU[C/T]_1 (1=Active 0=Inactive) PLL202-108 Rev 8/20/02 Page 6 ...
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... PCI1 (1=Active 0=Inactive) 1 PCI2 (1=Active 0=Inactive) 1 PCI3 (1=Active 0=Inactive) 1 PCI4 (1=Active 0=Inactive) 1 PCI5 (1=Active 0=Inactive) 1 PCI6 (1=Active 0=Inactive) Description 1 PCI7 (1=Active 0=Inactive) 1 PCI8 (1=Active 0=Inactive) 1 HTT[C/T]0 (1=Active, 0=Inactive) 1 HTT[C/T]1 (1=Active, 0=Inactive) 1 (Reserved) 1 (Reserved) 1 REF1 (1=Active, 0=Inactive) 1 REF0 (1=Active, 0=Inactive) PLL202-108 Rev 8/20/02 Page 7 ...
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... Linear programming sign bit ( 0 is “+” “−” Linear programming magnitude bit 6 (MSB) 0 Linear programming magnitude bit 5 0 Linear programming magnitude bit 4 0 Linear programming magnitude bit 3 0 Linear programming magnitude bit 2 0 Linear programming magnitude bit 1 0 Linear programming magnitude bit 0 (LSB) PLL202-108 Description Rev 8/20/02 Page 8 ...
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... Dog falls back to fall back frequency setting in Byte 8. 0 Watchdog Time Interval Bit 5 (MSB) 0 Watchdog Time Interval Bit 4 0 Watchdog Time Interval Bit 3 0 Watchdog Time Interval Bit 2 0 Watchdog Time Interval Bit 1 0 Watchdog Time Interval Bit 0 (LSB) PLL202-108 Description Description Rev 8/20/02 Page 9 ...
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... Enable VCO-N Counter programming (byte21~22 programming through setting I2C byte 21~22 0= programming through Frequency ROM setting 1 Spread Spectrum mode selection. 1=Center Spread, 0= Down Spread Center Spread: SST<6:0> = Modulation rate * Down Spread: SST<6:0> = Modulation rate * N / PLL202-108 Description Description Rev 8/20/02 Page 10 ...
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... These three bits will adjust timing of HTTT_1/HTTC_1 clock signals either positive or negative delay up to +640ps or –480ps 1 with ±160ps per step and ± 5% accuracy. 1 PLL202-108 Setting applies to the following outputs: 1. HTT 2. AGP 3. All PCI Description Description ...
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... Setting II +50% +38% Setting applies to the +25% following outputs +13% 1. PCIF,PCI[5:8] Default 2. PCI[0:4] 3. REF[0:1] -13% -25% -38% Default 0 Reserved. 0 Reserved. 0 Reserved. 0 Reserved. 0 Reserved. 0 These three bits will program drive strength for all AGP clocks 1 output clock (see Table 2). 1 PLL202-108 Description Description Rev 8/20/02 Page 12 ...
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... Table 2). 1 Default 0 Reserved. 0 Reserved. 0 These three bits will program drive strength for PCI[0:4] output 1 clocks (see Table 2 These three bits will program drive strength for REF[0:1] output 1 clocks (see Table 2). 1 PLL202-108 Description Description Rev 8/20/02 Page 13 ...
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... These four bits will program VCO divider for CPUT_0 and CPUC_0 clocks (see Table 3 These four bits will program VCO divider for CPUC_1 and CPUT_1 clocks (see Table 3 PLL202-108 Low Speed Divider Default ROM Selection N/A /30 N/A /32 /24 1. PCIF,PCI /20 2 ...
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... These four bits will program VCO divider for all PCI clocks (see Table 3 These four bits will program VCO divider for all AGP clocks (see Table 3 Default 1 1 (Reserved These four bits will program VCO divider all AGP clocks (see Table 3 PLL202-108 Description Description Rev 8/20/02 Page 15 ...
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... Name Default Bit 7 N<7> Bit 6 N<6> Bit 5 N<5> Bit 4 N<4> Bit 3 N<3> Bit 2 N<2> Bit 1 N<1> Bit 0 N<0> 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 VCO(MHz)= N<15:0> * 14.318/ 512 VCO(MHz)= N<15:0> * 14.318/ 512 PLL202-108 Description Description Rev 8/20/02 Page 16 ...
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... Once Enabled, WDT has to be disabled within a period that is shorter than the programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog reset pulse to provoke a system reset. After system restarts, the PLL202-108 will start from predefined Fall-back Frequency if system for any reason fails again at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery ...
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... I2C Register Loading: WD-TIMER, WD-ENABLE Disable WD- SUCCESS F = Target CPU Copy Fall-Back SUCCESS Disable WD Fall-Back CPU Frequency Setting PLL202-108 START Fall-Back, M, Wait For System Response FAIL - After specified WD-Timer Expired System Restart @ Fall-back Frequency FAIL - After specified WD-Timer Expired System Restart @ ...
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... C =0 pF@133MHz, 3.3V±5% DDL pF@66MHz, 2.5V± pF@133MHz, 2.5V±5% DDL crossing of target Freq. st trans 3. Logic Inputs IN C XIN & XOUT pins INX PLL202-108 MIN. MAX 0 0 0 -65 ...
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... PCI, AGP Assumes full supply CPU,PCIF,PCI, voltage reached within APIC,AGP,REF, 1ms from power-up. Short 48MHz,24MHz cycle exist prior to frequency stabilization. CPU V =3.3V(2.5V)±5% DD PCI,AGP V =3.3V±5% DD REF,48MHz,24MHz V =3.3V±5% DD PLL202-108 = 0°C to 70°C A MIN. TYP Rev 8/20/02 Page 20 MAX. UNITS 1 1 ...
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... MIN (0.203 - 0.406) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202-108 X C PLL202-108 0.025 0.635 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...