PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 11

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

TABLE 1: Output Signals SKEW Programming Summary:
13. Byte 12: SKEW Control Register
14. Byte 13: SKEW Control Register
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Bit<2:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
111
110
101
100
011
010
001
000
CPU0
CPU1
HTT0
HTT1
Default
Skew
Skew
Skew
Skew
+320ps
+240ps
+160ps
-160ps
-240ps
+80ps
-80ps
Skew Setting I (±80ps/step)
CPU-PCI
Name
Name
Skew
-
-
Programmable Clock Generator for ALI 1681 P4 Chip Sets
Setting applies to the following
outputs:
1. CPU0
2. CPU1
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Default
Default
0
0
0
1
1
0
1
1
1
0
0
1
1
0
1
1
Reserved.
Reserved.
These three bits will adjust timing of CPU_Host signals
(CPUT_0/CPUC_0) either positive or negative delay up to +320ps
or –240ps with ±80ps per step and ± 5% accuracy.
These three bits will adjust timing of CPU_chip_sets signals
(CPUT_1/CPUC_1) either positive or negative delay up to +320ps
or –240ps with ±80ps per step and ± 5% accuracy.
Skew setting between CPU and PCI clocks
Bit[7:6]: 00 = 0.5 ns,
These three bits will adjust timing of HTTT_0/HTTC_0 signal
either positive or negative delay up to +640ps or –480ps with
±160ps per step and ± 5% accuracy.
These three bits will adjust timing of HTTT_1/HTTC_1 clock
signals either positive or negative delay up to +640ps or –480ps
with ±160ps per step and ± 5% accuracy.
01 = 1.3 ns,
10 = 2 ns (default)
11 = 2.5ns
Default
+640ps
+480ps
+320ps
+160ps
-160ps
-320ps
-480ps
Skew Setting II (±160ps/step)
Description
Description
Setting applies to the following
outputs:
1. HTT
2. AGP
3. All PCI
PLL202-108
Rev 8/20/02 Page 11