PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 15
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PLL202-108
Manufacturer Part Number
PLL202-108
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL202-108.pdf
(21 pages)
20. Byte 19: VCO Divider Control Register
21. Byte 20: VCO Divider Control Register
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Divider
Divider
Divider
AGP
HTT
PCI
Name
Name
-
-
-
-
Programmable Clock Generator for ALI 1681 P4 Chip Sets
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Default
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
These four bits will program VCO divider for all PCI clocks (see
Table 3).
These four bits will program VCO divider for all AGP clocks (see
Table 3).
(Reserved)
These four bits will program VCO divider all AGP clocks (see
Table 3).
Description
Description
PLL202-108
Rev 8/20/02 Page 15