PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 17

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PROGRAMMING OF CPU FREQUENCY
To simplify traditional loop counter setting, the PLL202-108 device incorporates SMART-BYTE ™ and
AccuVCO technology with one single variable programming via I2C. Detail of PLL202-108's tri-mode
frequency programming method is described below:
1. ROM-table Frequency Programming:
2. Micro-step Linear Frequency Programming:
3. VCO Frequency Programming:
BUILT-IN WATCHDOG TIMER (WDT)
Watchdog timer is used to perform safe recovery if frequency switching causes system to enter into
“Hang-up” state within a reasonable period of time (or Watchdog time interval). While disabled, the
watchdog time interval can be programmed between 250ms and 256 seconds by setting the timer unit
and timer interval. Once Enabled, WDT has to be disabled within a period that is shorter than the
programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog reset pulse to
provoke a system reset. After system restarts, the PLL202-108 will start from predefined Fall-back
Frequency if system for any reason fails again at Fall-back Frequency, the internal hardware will then
generate a watchdog reset to restart the system from the value of external hardware jumper setting to
ensure a safe recovery.
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The pre-defined 32 frequencies found in Frequency table can be accessed through external jumpers
or 5 bits I2C setting.
CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around
selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus
frequencies will be changed proportionally with the rate that CPU frequency changes.
Internal VCO frequency is defined as the function of N times a fixed constant of 0.028.
Programmable VCO divider via I2C in Table 3 or pre-defined VCO divider in Frequency table will then
determine the output CPU Frequency. Other bus frequencies will be changed proportionally with the
rate that CPU frequency changes. The formula is as follow:
Where:
Where:
Where:
Programmable Clock Generator for ALI 1681 P4 Chip Sets
1. M is a magnitude factor defined in I2C Byte 7.bit (0:6)
2. ± (sign bit) of M is defined in I2C Byte7.bit 7
3. α is defined in Frequency table or = 1.79/(VCO_Divider).
1. F
2. N (counter) is defined in I2C byte 21,22
1. VCO_divider is either predefined by frequency table or through I2C Byte 18-20
VCO
F
F
F
is limited in the range between 200(Mhz) to 1200(Mhz).
CPU
CPU
VCO
=
=
=
F
F
N
CPU.ROM-Table
VCO
*
0.028
÷ VCO_
±
divider
α
*
M
PLL202-108
Rev 8/20/02 Page 17