PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 6

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
2. BYTE 1: Control Register (1=Enable, 0=Disable)
3. BYTE 2: Control Register (1=Enable, 0=Disable)
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Bit
Pin#
Pin#
Pin#
43,44
39,40
33,34
29,30
43,44
39,40
22
26
27
23
22
22
27
26
5
8
6
5
8
6
-
-
-
-
Programmable Clock Generator for ALI 1681 P4 Chip Sets
Default
Default
Default
Power-up
FS3:FS0
Latched
value
X
X
X
X
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Description
FS3
FS2
FS1
FS0
Frequency selection bit 1=Via I2C, 0=Via External jumper
FS4
0=normal, 1= Spread Spectrum Enable
(Reserved)
Description
AGP1 (1=Active 0=Inactive)
AGP0 (1=Active 0=Inactive)
24_48MHz (1=Active, 0=Inactive)
48MHz (1=Active, 0=Inactive)
Inverted Power-up latched FS3 value (Read only)
Inverted Power-up latched FS2 value (Read only)
Inverted Power-up latched FS1 value (Read only)
Inverted Power-up latched FS0 value (Read only)
Description
CPU_STOP# setting for CPU[C/T]_0 (0=Free Running, 1=Stopped)
CPU_STOP# setting for CPU[C/T]_1 (0=Free Running, 1=Stopped)
CPU_STOP# setting for AGP0 (0=Free Running, 1=Stopped)
CPU_STOP# setting for AGP1 (0=Free Running, 1=Stopped)
CPU_STOP# setting for HTT[C/T]_0 (0=Free Running, 1=Stopped)
CPU_STOP# setting for HTT[C/T]_1 (0=Free Running, 1=Stopped)
CPU[C/T]_0 (1=Active 0=Inactive)
CPU[C/T]_1 (1=Active 0=Inactive)
PLL202-108
Rev 8/20/02 Page 6