ssd1325z Bolymin, Inc, ssd1325z Datasheet - Page 23

• Manufacturer Part Number: ssd1325z
• Description: 128 X 80, 16 Gray Scale Dot Matrix Oled/pled Segment/common Driver With Controller
• Manufacturer: Bolymin, Inc

8.3
This module is an On-Chip low power RC oscillator circuitry. The operation clock (CLK) can be
generated either from internal oscillator or external source CL pin. This selection is done by CLS pin. If
CLS pin is pulled HIGH, internal oscillator is chosen and CL should be left open. Pulling CLS pin LOW
disables internal oscillator and external clock must be connected to CL pins for proper operation. When
the internal oscillator is selected, its output frequency F
to
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor
“D” can be programmed from 1 to 16 by command B3h
The frame frequency of display is determined by the following formula.
where
•
•
•
•
If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency
leads to higher power consumption on the whole system.
8.4
This module determines whether the input data is interpreted as data or command. Data is interpreted
based upon the input of the D/C# pin.
If D/C# pin is HIGH, the input at D
LOW, the input at D
corresponding command register.
Solomon Systech
Table 18
D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from
1 to 16.
K is row period. It is configured by command B2h. This value should comply with following
condition.
Number of multiplex ratio is set by command A8h. The power ON reset value is 4Fh.
F
setting results in faster frequency.
OSC
Oscillator Circuit and Display Time Generator
Command Decoder and Command Interface
is the oscillator frequency. It can be changed by command B3h A[7:4]. The higher the register
.
CL
7
-D
0
Oscillator
is interpreted as a Command which will be decoded and be written to the
Internal
Fosc
K ≥ Phase 1 + Phase 2 + Phase 3 + GS15
7
F
-D
Figure 13 : Oscillator Circuit
FRM
0
is written to Graphic Display Data RAM (GDDRAM). If it is
=
DCLK = F
D
×
CLS
K
M
U
X
×
OSC
No.
F
OSC
CLK
osc
/ D
can be changed by command B3h, please refer
of
Mux
Oct 2007
Divider
P 23/60
Clock
Display
DCLK
Rev 1.9
SSD1325