PLL602-01 PhaseLink (PLL), PLL602-01 Datasheet - Page 3
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PLL602-01
Manufacturer Part Number
PLL602-01
Description
, 12 - 25MHz In, 24 - 50MHz Out, CMOS, 3.3V
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL602-01.pdf
(4 pages)
3. Jitter and Phase Noise specification
4. DC Specification
5. Crystal Specifications
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
ESD Protection
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
Driving power
ESR
PARAMETERS
PARAMETERS
PARAMETERS
SYMBOL
V
V
V
V
I
OHC
DD
at 44MHz, with capacitive de-
coupling between VDD and GND.
44MHz @100Hz offset
44MHz @1kHz offset
44MHz @10kHz offset
44MHz @100kHz offset
44MHz @1MHz offset
DD
OH
OL
SYMBOL
F
Ouput load of 10pF
I
I
I
At TTL level (High drive)
At TTL level (Low drive)
Human Body Model, all
pads except XT and XTB
Human Body Model, XT
and XTB pads
C
CONDITIONS
OH
LO
OH
XIN
F
L
R
XIN
(xtal)
= 12mA
= -12mA
= -4mA
S
= 12 - 25MHz
CONDITIONS
Low Phase Noise XO (24MHz to 50MHz)
MIN.
12
Preliminary for proposal
TYP.
20
1
MIN.
V
DD
MIN.
3000
2000
3.13
2.4
36
12
– 0.4
MAX.
25
30
TYP.
-110
-135
-130
-132
-80
7
TYP.
10
51
17
50
MAX.
UNITS
MHz
PLL602-01
mW
pF
MAX.
3.47
0.4
UNITS
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev 12/04/01 Page 3
ps
UNITS
mA
mA
mA
mA
V
V
V
V
V