PLL701-10 PhaseLink (PLL), PLL701-10 Datasheet

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PLL701-10

Manufacturer Part Number
PLL701-10
Description
, 1x to 8x Out, 15-30MHz In, 15-240MHz Out, SST
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
different levels of EMI reduction by selecting the
amplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
The chip operates with input frequencies ranging from
10 to 30 MHz and provides 1x to 8x at its output.
OUTPUT CLOCK (FOUT) SELECTION
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
M2
XOUT
0
0
0
0
1
1
1
1
M(0:2)
Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
10MHz to 240MHz output with output enable.
10MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
Reduced EMI from Spread Spectrum Modulation,
with selectable modulation amplitude for Center
Spread, Down Spread or Asymmetric Spread.
TTL/CMOS compatible outputs.
3.3V Operating Voltage.
100 ps maximum cycle-to-cycle jitter.
Available in 16-Pin 150mil SSOP or DIE.
XIN
M1
0
0
1
1
0
0
1
1
M0
XTAL
0
1
0
1
0
1
0
1
OSC
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
FIN/XIN
10 ~ 30
(MHz)
Control
Logic
PLL
SST
Multiplier
X1
X2
X3
X4
X5
X6
X7
X8
40 ~ 120
50 ~ 150
60 ~ 180
70 ~ 210
80 ~ 240
VDD
10 ~ 30
20 ~ 60
30 ~ 90
FOUT
(MHz)
FOUT
PACKAGE PIN CONFIGURATION
DIE PAD CONFIGURATION
Note: ^: Internal pull-up resistor (120k
XOUT/SD0*^
XOUT/SD0*^
GNDOSC
XIN/FIN
*: SD0 and SD1 are latched upon power-up.
SC2^
SC0^
SC1^
SC0^
SC1^
M2^
M1^
M0^
M2^
M1^
M0^
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
XIN/FIN = 10 ~ 30 MHz
Preliminary
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PLL701-10
GND
AVDD
REF/SD1*^
VDD
SC3^
OE^
FOUT
GND
for SD0, 30 k
Rev 11/04/02 Page 1
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
OE^
FOUT
GNDBUF
for SC0-

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PLL701-10 Summary of contents

Page 1

... Operating Voltage. 100 ps maximum cycle-to-cycle jitter. Available in 16-Pin 150mil SSOP or DIE. DESCRIPTIONS The PLL701- low EMI Clock Generator and Multiplier for high-speed digital systems. It uses Spread Spectrum Technology (SST) and permits different levels of EMI reduction by selecting the amplitude of the applied SST. The SST feature can be turned off ...

Page 2

... Fin / 512 2.750 3.000 3.250 3.500 3.750 0. PLL701-10 Preliminary Modulation Type C ± 0.125% C ± 0.25% C ± 0.375% C ± 0.50% D -1.00% C ± 0.625% A +0.125 ~ -1.125% C ± 0.75% A +0.25 ~ -1.25% C ± 0.875% A +0.375 ~ -1.375% C ± 1.00% A +0.50 ~ -1. ...

Page 3

... After the input sampling, this pin provides a B buffered Reference Clock Output of the same frequency as the crystal or clock input. 30k P 3.3V Analog power supply. P Ground for Oscillator circuitry. P Ground for output buffer circuitry. P Ground. PLL701-10 Preliminary Description internal pull- internal pull- internal pull- internal pull-up. Rev 11/04/02 Page 3 ...

Page 4

... Pin 11 is the output enable pin, that tri-states all outputs when low (logical “zero”). In order to reduce the number of pins on the chip, the PLL701-10 uses pin 2 and 14 (XOUT/SD0 and REF/SD1 bi-directional pin. The pins serve as modulation rate selector inputs (SD0 and SD1) upon power-up (see modulation rate table on page 1), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon as the inputs have been latched ...

Page 5

... =6mA, VDD=3. When using a crystal XIN F When using reference clock IN When using reference clock Between Pin XIN and C L XOUT* R PIN PIN 3,4,5,6,7,8,11, Load CC PLL701-10 Preliminary MIN. MAX 0 0 0 ...

Page 6

... Output Duty Cycle D Cycle to Cycle Jitter T cyc-cyc Cycle to Cycle Jitter T cyc-cyc 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 CONDITIONS T Measured at 0.8V ~ 2. Measured at 2.0V ~ 0. FOUT=48MHz @ 3.3V FOUT=72MHz @ 3.3V PLL701-10 Preliminary MIN. TYP. MAX. UNITS 0.8 0.95 1.1 0.78 0.85 0 100 100 Rev 11/04/02 Page 6 ns ...

Page 7

... PLL701-10 Preliminary Rev 11/04/02 Page 7 ...

Page 8

... A1 0.025 BASIC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL701- PLL701-10 Preliminary TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP; D=DIE ...

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