h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 584
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
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Section 19 Host Interface LPC Interface (LPC)
Figure 19.1 shows a block diagram of the LPC.
Rev. 3.00 Mar 21, 2006 page 530 of 788
REJ09B0300-0300
LAD0–
LAD3
Legend:
HICR0 to HICR3: Host interface control registers 0 to 3
LADR3H, 3L:
IDR1 to IDR3:
ODR1 to DOR3: Output data registers 1 to 3
STR1 to STR3:
TWR1–15
TWR1–15
TWR0MW
TWR0SW
Cycle detection
Serial
Serial
LPC channel 3 address register 3H and 3L
Input data registers 1 to 3
Status registers 1 to 3
SYNC output
parallel conversion
parallel conversion
H'0060/64
H'0062/66
LADR3
ODR3
ODR2
ODR1
STR3
STR2
STR1
IDR3
IDR2
IDR1
Figure 19.1 Block Diagram of LPC
Address match
Module data bus
Internal interrupt
Control logic
Parallel
SIRQCR0
SIRQCR1
TWR0MW:
TWR0SW:
TWR1 to TWR15: Two-way data registers 1 to 15
SERIRQ0, 1:
HISEL:
control
HICR0
HICR1
HICR2
HICR3
HISEL
serial conversion
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PMEE
PMEB
PME input
Two-way register 0MW
Two-way register 0SW
SERIEQ control registers 0 and 1
Host interface select register
IBFI1
IBFI2
IBFI3
ERRI
PB1 I/O
PB0 I/O
P80 I/O
SERIRQ
CLKRUN
LPCPD
LFRAME
LRESET
LCLK
LSCI
LSMI
PME
GA20
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