h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 369

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

13.4.9
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
• Internal latches used to retain register read information for setting/clearing flags in ICMR,
• The value of the ICMR bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
• Basically, other register flags are not cleared either, and so flag clearing measures must be
• When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not
• Similarly, when clearing is required again, all the bits must be written to simultaneously in
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
output, etc.)
and ICDRF flags), and PGCTL)
ICCR, and ICSR
taken as necessary.
taken as necessary.
retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR.
accordance with the setting.
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
Initialization of Internal State
Rev. 1.00, 05/04, page 335 of 544