h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 481

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Note: Use a z3 µs write pulse for additional programming.
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if
Note 7: Write Pulse Width
Reprogram Data Computation Table
Number of Writes n
Original Data
(D)
0
0
1
1
Write pulse application subroutine
Wait (z1) µs, (z2) µs or (z3) µs
Reprogram data storage
Additional-programming
Program data storage
Clear PSU bit in FLMCR2
Sub-Routine Write Pulse
1000
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of z1 µs or z2 µs is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in section 22.5, Flash Memory Characteristics.
Set PSU bit in FLMCR2
998
999
Clear P bit in FLMCR1
data storage area
10
11
12
13
area (128 bytes)
area (128 bytes)
Set P bit in FLMCR1
1
2
3
4
5
6
7
8
9
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a z3 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
(128 bytes)
Disable WDT
WDT enable
Wait (α) µs
Wait (β) µs
Wait (γ) µs
RAM
End Sub
0
1
0
1
Verify Data
(V)
Write Time (z) µs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
1
0
1
1
Reprogram Data
(X)
Figure 18.9 Program/Program-Verify Flowchart
* 5
Increment address
Comments
Still in erased state; no action
Programming completed
Programming incomplete;
reprogram
NG
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Apply write pulse (Additional programming)
Store 128-byte program data in program
data area consecutively to flash memory
Transfer reprogram data to reprogram data area
Write 128-byte data in RAM reprogram
Transfer additional-programming data to
Additional-programming data computation
data area and reprogram data area
H'FF dummy write to verify address
additional-programming data area
Apply write pulse z1 µs or z2 µs
Reprogram data computation
data verification completed?
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read verify data
Write data =
verify data?
Wait (η) µs
Wait (x) µs
Wait (γ) µs
Wait (ε) µs
Wait (θ) µs
OK
OK
128-byte
START
OK
m = 0 ?
6 ≥ n ?
m = 0
6 ≥ n?
n = 1
Sub-Routine-Call
OK
OK
Additional-Programming Data Computation Table
Reprogram Data
(X')
0
0
1
1
NG
NG
NG
NG
m = 1
Verify Data
(V)
0
1
0
1
* 4
* 3
* 4
* 1
* 3
* 2
* 4
* 1
See Note 7 for pulse width
Rev. 1.00, 05/04, page 447 of 544
µs
Clear SWE bit in FLMCR1
Programming failure
Additional-
Programming Data (Y)
0
1
1
1
Wait (θ) µs
n ≥ (N)?
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
OK
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Comments
NG
n ← n + 1