h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 49

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Table 14.9
Table 14.10 HSYNCO Output Modes........................................................................................ 370
Table 14.11 VSYNCO Output Modes........................................................................................ 371
Section 15 Watchdog Timer (WDT)
Table 15.1
Table 15.2
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Table 16.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 418
Table 16.11 SSR Status Flags and Receive Data Handling........................................................ 428
Table 16.12 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 458
Table 16.13 SCI Interrupt Sources ............................................................................................. 460
Table 16.14 SCI Interrupt Sources ............................................................................................. 460
Section 17 I
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Table 17.8
Table 17.9
Table 17.10 IIC Interrupt Sources .............................................................................................. 540
Table 17.11 I
Table 17.12 Permissible SCL Rise Time (t
Table 17.13 I
Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF,
and TOCR Settings................................................................................................. 368
Pin Configuration ................................................................................................... 375
WDT Interrupt Source............................................................................................ 382
Pin Configuration ................................................................................................... 391
Relationships between N Setting in BRR and Bit Rate B ...................................... 405
BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 406
Maximum Bit Rate for Each Frequency (Asynchronous Mode) ............................ 409
Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................. 409
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 410
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 410
BRR Settings for Various Bit Rates
(Smart Card Interface Mode, n = 0, s = 372).......................................................... 411
Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) ... 411
Pin Configuration ................................................................................................... 476
Communication Format.......................................................................................... 481
I
Flags and Transfer States ....................................................................................... 490
Restrictions on Accessing IIC Registers ................................................................ 511
Operation Reservation Commands......................................................................... 513
Operation When the Operation Reservation Command Is Completed ................... 514
Examples of Operation Using DTC ....................................................................... 532
Examples of Operation Reservation Adapter Operation Using DTC..................... 533
2
2
2
2
C Bus Interface (IIC)
C Transfer Rate.................................................................................................... 484
C Bus Timing (SCL and SDA Outputs) .............................................................. 541
C Bus Timing (with Maximum Influence of t
sr
) Values................................................................. 542
Rev. 3.00 Jan 25, 2006 page xlix of lii
Sr
/t
Sf
) ............................................. 543