h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 106

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

5.6.1
In interrupt control mode 0, interrupt requests other than NMI and address break are masked by
ICR and the I bit of the CCR in the CPU. The interrupt requests are held pending when the I bit is
set to 1. Figure 5.4 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 2.00, 03/04, page 74 of 534
interrupt request is sent to the interrupt controller.
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
interrupts.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Mode 0