h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 108
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 108 of 570
- Download datasheet (5Mb)
5.6.2
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
The interrupt requests are held pending when the I bit is set to 1.
1. An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
2. An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set
to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts
are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown
below. Figure 5.5 shows a state transition diagram.
1. All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 >
2. Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
3. Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
Rev. 2.00, 03/04, page 76 of 534
to 0. When the I bit is set to 1, the interrupt request is held pending.
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
IRQ1 > address break …)
0.
Exception handling execution
Interrupt Control Mode 1
All interrupt requests
or I
are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1
1, UI
1
I
interrupt requests are accepted
Only NMI and address break
0
I
1, UI
I
0
0
UI
0
interrupt control level 1 interrupt
Exception handling
Only NMI, address break, and
execution or UI
requests are accepted
1
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