h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 156

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

6.6.5
Figure 6.22 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and two T
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE) pin of the DRAM.
Rev. 2.00, 03/04, page 124 of 534
Read
Write
Basic Timing
Figure 6.22 DRAM Basic Access Timing (RAST = 0, CAST = 0)
φ
Address bus
Data bus
Data bus
(
(
(
(
(
,
)
)
)
)
)
c1
and T
c2
T
(column address output cycle) states.
p
Row address
High
High
p
T
(precharge cycle) state, one T
r
T
c1
Column address
T
c2
r
(row address