h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 176
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 176 of 570
- Download datasheet (5Mb)
Read after Write: If an external read occurs after an external write while the IDLE1 and IDLE0
bits in BCR are set to B'11, an idle cycle which is set by the IDLC1 and IDLC0 bits in BCR is
inserted at the start of the read cycle.
Figure 6.46 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a collision occurs in bus cycle B between the CPU write data and read data from the SRAM.
In (b), an idle cycle is inserted, and a data collision is prevented.
Rev. 2.00, 03/04, page 144 of 534
Address bus
Data bus
(area A)
(area B)
φ
Figure 6.45 Example of Idle Cycle Operation (Write after Read)
T
1
(a) No idle cycle insertion
Bus cycle A
Long output floating time
(IDLE1 = 0, IDLE0 = 0)
T
2
y
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
Data bus
(area A)
(area B)
φ
(b) Idle cycle insertion
T
1
Bus cycle A
(IDLE1 = 0, IDLE0 = 0, IDLC1 = 0,
IDLC0 = 0)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2
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