h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 204

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

The transfer mode can be set independently for each channel. In normal transfer mode, a one-byte,
one-word, or one-longword transfer is executed in response to one transfer request. With auto
requests, burst or cycle steal transfer mode can be set. In normal or burst transfer mode,
continuous, high-speed transfer can be performed until the specified number of transfers have been
executed or the transfer enable bit is cleared to 0. In block transfer mode, a transfer of the
specified block size is executed in response to one transfer request. The block size can be from 1
to 256 bytes, words, or longwords. Within a block, transfer can be performed at the same high
speed as in burst transfer mode. When the “no specification” setting (DMTCR = H'000000) is
made for the number of transfers, the transfer counter is halted and there is no limit on the number
of transfers, allowing transfer to be performed endlessly.
Incrementing or decrementing the memory address by 1, 2, or 4, or leaving the address unchanged,
can be specified independently for each address register. In all transfer modes, it is possible to set
a repeat area comprising a power-of-two number of bytes.
7.4.2
Address Modes (Dual Address Mode/Single Address Mode)
Dual Address Mode: In dual address mode, both the transfer source and transfer destination are
specified by registers in the DMAC, and one transfer is executed in two bus cycles.
The transfer source address is set in the source address register (DMSAR), and the transfer
destination address is set in the destination address register (DMDAR).
In a transfer operation, the value in external memory specified by the transfer source address is
read in the first bus cycle, and is written to the external memory specified by the transfer
destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by an
internal bus master or refresh cycle) does not occur between these two cycles.
TEND pin output can be enabled or disabled by means of the TENDE bit in DMMDR. TEND is
output for two consecutive bus cycles. The DACK signal is not output.
Figure 7.2 shows an example of the timing in dual address mode.
Rev. 2.00, 03/04, page 172 of 534