h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 245

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the DA bit to 1 in DMMDR. If the BEF bit
is 1 in DMMDR, transfer can be resumed from midway through a block.
Hardware Standby Mode and Reset Input: The DMAC is initialized in hardware standby mode
and by a reset. DMA transfer is not guaranteed in these cases.
7.4.13
The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle or
internal bus master (CPU) access cycle never occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh
may be inserted after the write cycle. As the CPU has lower priority than the DMAC, the CPU
access is not executed until the DMAC releases the bus.
The DMAC releases the bus in the following cases:
1. When DMA transfer is performed in cycle steal mode
2. When switching to a different channel
3. When transfer ends in burst transfer mode
4. When transfer of one block ends in block transfer mode
7.5
DMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 7.4 shows the interrupt sources and their priority.
Table 7.4
Interrupt
DMTEND0
DMTEND1
DMTEND2
DMTEND3
Relationship between DMAC and Other Bus Masters
Interrupt Sources
Interrupt Sources and Priority Order
Interrupt source
Transfer end indicated by channel 0 transfer counter
Channel 0 source address repeat area overflow
Channel 0 destination address repeat area overflow
Transfer end indicated by channel 1 transfer counter
Channel 1 source address repeat area overflow
Channel 1 destination address repeat area overflow
Transfer end indicated by channel 2 transfer counter
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Rev. 2.00, 03/04, page 213 of 534
Interrupt Priority
High
Low