h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 71

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

Table 2.10 Block Data Transfer Instructions
2.6.2
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
• Register field
• Effective address extension
• Condition field
Instruction
EEPMOV.B
EEPMOV.W
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
Size


Function
if R4L ≠ 0 then
else next:
if R4 ≠ 0 then
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Repeat @ER5+ → @ER6+
Until R4L = 0
Repeat @ER5+ → @ER6+
Until R4 = 0
R4L–1 → R4L
R4–1 → R4
Rev. 2.00, 03/04, page 39 of 534