AM186ER-25KCW AMD [Advanced Micro Devices], AM186ER-25KCW Datasheet - Page 110

• Manufacturer Part Number: AM186ER-25KCW
• Description: High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM
• Manufacturer: AMD [Advanced Micro Devices]

PLL, 44
power consumption calculation, 62
power savings, 59
power-save mode
power-save operation, 48
PQFP connection diagram and pinouts
PQFP physical dimensions, 105
PQFP pin assignments
programmable I/O (PIO) pins, 57
programming
pseudo static RAM
PSRAM
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM read cycle waveforms, 80
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM refresh cycle waveforms, 86
PSRAM write cycle
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
RAM
RD, 35
read cycle waveforms, 72
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
ready and wait-state programming, 49
refresh control unit, 53
related documents, 13
RES, 35
reset
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
Index-4
clock waveforms, 95
Am186ER, 22
Am188ER, 25
Am186ER
Am188ER
interrupt control unit, 53
ready and wait-state, 49
support, 44
support, 44
waveforms, 83
interaction with external, 52
initialization and processor, 48
sorted by pin name, 24
sorted by pin number, 23
sorted by pin name, 27
sorted by pin number, 26
R
Am186™CC Communications Controller Data Sheet
reset configuration register, 48
reset waveforms, 100
revision history, 10
RFSH2/ADEN, 35
RXD/PIO28, 35
S0/SREN, 37
S1/IMDIS, 37
S2, 35
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
serial ports
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
software halt cycle waveforms, 91
source clock
SRDY/PIO6, 38
SSI, 102
support, 13
switching characteristics
related signals, 100
DMA transfers, 55
external, 45
multiple read, 58
multiple write, 58
waveforms, 103
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
commercial, 67
industrial, 67
internal RAM show read cycle (25 and 33 MHz), 76
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
read cycle (25 and 33 MHz), 70
read cycle (40 and 50 MHz), 71
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
S