AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 31

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

B28
Preliminary Technical Data
WRITE SYSTEM CONTROL REGISTER
The System Control Register is accessed when the PMU channel address PMU3-PMU0 and Mode Bits, MODE1 and MODE0 are all
zeros. It allows quick setup of different functions within the device. The System Control Register operates on a per device basis.
Table 15. System Control Register Bits
Table 16. System Control Register Functions
Bit
28
(MSB)
27
26
25
24
23
22
SYSTEM CONTROL REGISTER SPECIFIC BITS
21
20
19
18
17
16
15
14
13
12
11
10
9
B27
Bit name
RD/ WR
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
CL3
CL2
CL1
CL0
CPOLH3
CPOLH2
CPOLH1
CPOLH0
GUARD ALM
CLAMP ALM
INT10K
CPBIASEN
DUTGND/CH
B26
B25
B24
When low, a write function takes place to the selected register, while if the RD/ WR bit is set high, this initiates a readback sequence
of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
Bits PMU3 through PMU0 address each of the PMU channels in the device. If all four of these bits are set to zero, the System Control
Register is addressed.
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set to
Zero to access the System Control Register.
Current Clamp Enable. Bits CL3 through CL0 enable and disable the current clamp function per channel. A “0” disables, while a “1”
enables. The clamp enable function is also available in the PMU register on a per channel basis. This dual functionality allows
flexible enable or disabling of this function. When reading back information on the status of the clamp enable function, what was
most recently written to the current clamp register is available in the readback word from either PMU or System Control Registers.
The Voltage clamps (FI mode) are always enabled.
Comparator Output Enable. By default the comparator outputs are hi-Z on power on. A “1” in each bit position enables the
comparator output for the selected channel. The CPBIASEN (Bit 13) must be enabled to power on the comparator functions. The
comparator enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator enable function, what was
most recently written to the comparator register is available in the readback word from either PMU or System Control Registers.
Comparator Enable. By default the comparators are powered down on power on. To enable the comparator function for all
channels, write a “1” to the CPBIASEN bit. A “0” disabled the comparators and shuts them down. Comparator Output Enables bits
(CPOLHx) allow the user to switch on each comparator output individually, enabling bussing of comparator outputs.
DUTGND per channel enable. The GUARDIN(0-3) /DUTGND(0-3) pins are shared pin functions and may be configured to enable a
DUTGND per PMU channel or GUARD input per PMU channel. Setting this bit to “1” enables DUTGND per channel. In this mode, this
pin now functions as a DUTGND pin on a per channel basis. The guard inputs are disconnected from this pin and instead connected
directly to the MEASVH line by an internal connection. Default power on condition is GUARDIN(0-3).
Clamp and Guard Alarm Function share one open drain CGALM alarm pin. By default, the CGALM pin is disabled. Bits GUARD ALM
and CLAMP ALM allow the user to choose if they only wish to have both or either information flagged to the CGALM pin. Set high to
enable either alarm function.
Internal Sense Short, INT10K. Setting this bit high allows the user to connect in an internal sense short resistor of 10kΩ between the
FOH and the MEASVH lines, (closes SW 7), it also closes SW 15, connecting another 10 kΩ resistor between DUTGND and AGND.
Description
B27
PMU3
0
0
0
0
0
-
1
-
1
1
MODE1
0
0
1
1
B23
B22
B26
PMU2
0
0
0
0
1
-
0
-
1
1
MODE0
0
1
0
1
B21
B25
PMU1
0
0
1
1
0
-
0
-
1
1
B20
Action
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x1)
B19
B24
PMU0
0
1
0
1
0
-
0
-
0
1
B18
B17
B23
MODE1
0
Select DAC or PMU Registers.
See below
Rev. PrM | Page 31 of 48
B16
B15
B22
MODE0
0
B14
B13
B12
SELECTED REGISTER
CH3
Write to System Control Register
×
×
×
×
-
CH3
-
CH3
CH3
B11
CH2
×
×
×
CH2
-
×
-
CH2
CH2
B10
B9
CH1
×
CH1
CH1
×
-
×
-
CH1
CH1
B8
B7
CH0
CHO
×
CH0
×
-
×
-
×
CH0
B6
B5
B4
AD5522
B3
B2
B1/0