AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 38

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

AD5522
READBACK OF SYSTEM CONTROL REGISTER
The readback function is a 24 bit word, mode, address and System Control Register data bits as shown in the following table.
Table 23. Readback System Control Register Data
Bit
23 (MSB)
22
SYSTEM CONTROL REGISTER SPECIFIC READBACK BITS
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
Bit name
MODE1
MODE0
CL3
CL2
CL1
CL0
CPOLH3
CPOLH2
CPOLH1
CPOLH0
CPBIASEN
DUTGND/CH
GUARD ALM
CLAMP ALM
INT10K
GUARD EN
GAIN1
GAIN0
TMP ENABLE
TMP1
TMP0
LATCHED
Unused Readback bits
0
0
Readback the status of the individual Clamp Enable bits. A “0” means the clamp is disabled, while a “1” enabled.
The clamp enable function is also available in the System Control Register. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the clamp enable function,
what was most recently written to the clamp register from either System Control register or PMU register will be
available in the readback word.
Readback information on the Comparator Output Enable status. A “1” signifies the function is enabled, while a
“0” disabled. A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The
comparator output enable function is also available in the PMU Register. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator output
enable function, what was most recently written to the comparator register from either System Control register
or PMU register will be available in the readback word.
This readback bit tells the status of the Comparator Enable function. A “1” in this bit position means the
Comparator functions are enabled, while a “0” disabled.
DUTGND per channel enable. If this bit is set at “1”, DUTGND per channel is enabled, while if “0”, individual
guard inputs are available per channel.
These bits give status on which of these alarm bits trigger the CGALM pin.
and AGND. If low, they are disconnected.
Readback status of the Guard amplifies. If high, Amplifiers are enabled.
Status of the selected MEASOUT Output Range.
Information is available on the status of the setting for Thermal shutdown function. Refer to System control
write register.
outputs, while if low, they are unlatched.
Will be loaded with zeros.
Description
If this bit is set high, the internal 10k resistor is connected between FOH and MEASVH, and between DUTGND
This bit tells of the status of the open drain outputs. When high, the open drain alarm outputs are latched
Rev. PrM | Page 38 of 48
Preliminary Technical Data