AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 41

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
POWER ON DEFAULT
The power on default for all DAC channels is that the contents of each m register is set to full-scale (0xFFFF) and c register to
midscale(0x8000). The contents of the DAC registers are :
Offset DAC: 0xA492, FIN DACs: 0x8000, CLL DACs: 0x0000, CLH DACs: 0xFFFF, CPL DACs: 0x0000, CPH DACs: 0xFFFF
The power on default for the Alarm Status Register is 0xFFFFF0, while the Comparator Status registers powers up at 0x400000. The
power on defaults of the PMU register and the System Control Register are shown below.
Table 28. Power on Default for System Control Register and PMU Register
Bit
21 (MSB)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
SYSTEM CONTROL REGISTER POWER ON DEFAULT
Bit name
CL3
CL2
CL1
CL0
CPOLH3
CPOLH2
CPOLH1
CPOLH0
CPBIASEN
DUTGND/CH
GUARD ALM
CLAMP ALM
INT10K
GUARD EN
GAIN1
GAIN0
TMP ENABLE
TMP1
TMP0
LATCHED
Unused Data Bits
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Rev. PrM | Page 41 of 48
CH EN
C2
C1
C0
MEAS1
MEAS0
PMU REGISTER POWER ON DEFAULT
Bit name
FORCE1
FORCE0
RESERVED
FIN
SFO
SSO
CL
CPOLH
COMPARE V/I
LTMPALM
TMPALM
Unused Data Bits
0
Description
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
AD5522