AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 9

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
TABLE 2. TIMING CHARACTERISTICS
AV
(T
SPI INTERFACE (
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LVDS INTERFACE (
Parameter
t
t
t
t
t
t
t
t
1
2
3
4
5
SDO output gets slower with lower DV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
All input signals are specified with t
See
This is measured with load circuit of
Guaranteed by design and characterization, not production tested.
3
1 DAC X1
2 DAC X1
3 DAC X1
4 DAC X1
Other Regs
4, 5
J
DD
= +25 to +90
Figure 5
≥
10V, AV
1, 2, 3
1, 2, 3
and
Figure 6
o
SS
Figure 5
C, max specs unless otherwise noted.)
Limit at TMIN, TMAX
595
20
8
8
10
15
5
5
4.5
30
1.25
1.75
2.25
2.75
270
20
20
150
0
100
10
300
100
25
45
60
Limit at TMIN, TMAX
10
4
2
2
2
2
TBD
TBD
≤ −
Figure 7
5V, |AV
and
)
Figure 6
r
DD
= t
Figure 4
CC
– AV
f
= 2 ns (10% to 90% of V
supply and may require use of slower SCLK.
)
SS
|
≥
20V and
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
µs max
µs max
µs max
µs max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
µs max
ns min
ns max
ns max
ns max
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
≤
CC
) and timed from a voltage level of 1.2 V.
33V, DV
Rev. PrM | Page 9 of 48
Description
Single channel write time
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
SYNC Falling Edge to SCLK Falling Edge Setup Time.
Minimum SYNC High Time.
29th SCLK Falling Edge to SYNC Rising Edge.
Data Setup Time.
Data Hold Time.
SYNC Rising Edge to BUSY Falling Edge.
BUSY Pulse Width Low
BUSY Pulse Width Low
BUSY Pulse Width Low
BUSY Pulse Width Low
BUSY Pulse Width Low
BUSY Pulse Width Low, System Control Register/PMU Register/M or C Registers
29
LOAD pulse width low
BUSY rising edge to FOH Output Response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FOH Output Response time
RESET Pulse Width Low.
RESET Time Indicated by BUSY
Minimum SYNC High Time in Readback Mode.
DV
DV
DV
Description
SCLK Cycle Time.
SCLK Pulse Width High and Low Time.
SYNC to SCLK Setup Time.
Data Setup Time.
Data Hold Time.
SCLK to SYNC Hold Time.
SCLK Rising Edge to SDO Valid.
SYNC high time
th
CC
CC
CC
CC
SLCK Falling EDGE to LOAD Falling Edge
= 2.3V to 5.25V, V
= 5V to 5.25V, SCLK Rising Edge to SDO Valid.
= 3V to 3.7V, SCLK Rising Edge to SDO Valid
= 2.3V to 3V, SCLK Rising Edge to SDO Valid
REF
=5V
Low.
AD5522