PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 115

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bits 7,6 - Reserved
6.3 ENHANCED PARALLEL PORT (EPP) MODES
EPP modes allow greater throughput than SPP modes by
supporting faster transfer times (8, 16 or 32-bit data trans-
fers in a single read or write operation) and a mechanism
that allows the system to address peripheral device regis-
ters directly. Faster transfers are achieved by automatically
generating the address and data strobes.
The connector pin assignments for these modes are listed
in Table 6-12 on page 134.
EPP modes support revision 1.7 and revision 1.9 of the
IEEE 1284 standard, as shown in Table 6-1.
In Legacy mode, EPP modes are supported for a parallel
port whose base address is 278h or 378h, but not for a par-
allel port whose base address is 3BCh. (There are no EPP
registers at 3BFh.) In both Legacy and Plug and Play
modes, bits 2, 1 and 0 of the parallel port base address
must be 000 in EPP modes.
SPP-type data transactions may be conducted in EPP
modes. The appropriate registers are available for this type
of transaction. (See Table 6-5.) As in the SPP modes, soft-
ware must generate the control signals required to send or
receive data.
6.3.1
Table 6-5 lists the EPP registers. All are single-byte regis-
ters.
Bits 0, 1 and 3 of the CTR register must be 0 and bit 2 must
be 1 before the EPP registers can be accessed, since the
signals controlled by these bits are controlled by hardware
during EPP accesses. Once these bits are set to 0 by the
software driver, multiple EPP access cycles may be in-
voked.
When EPP modes are enabled, the software can perform
SPP Extended mode cycles. In other words, if there is no
access to one of the EPP registers, EPP Address (ADDR)
or EPP Data Registers 0-3 (DATA0-3), EPP modes behave
like SPP Extended mode, except for the interrupt, which is
pulse triggered instead of level triggered.
Bit 7 of STR (BUSY status) must be set to 1 before writing
to DTR in EPP modes to ensure data output to PD7-0.
The enhanced parallel port monitors the IOCHRDY signal
during EPP cycles. If IOCHRDY is driven low for more then
10
cycle by asserting IOCHRDY, thus releasing the system
from a stuck EPP peripheral device. (This time-out event is
only functional when the clock is applied to this logical de-
vice).
When the cycle is aborted, ASTRB or DSTRB becomes in-
active, and the time-out event is signaled by asserting bit 0
of STR. If bit 4 of CTR is 1, the time-out event also pulses
the IRQ5 or IRQ7 signals when enabled. (IRQ5 and IRQ7
can be routed to any other IRQ lines via the Plug and Play
block).
EPP cycles to the external device are activated by invoking
read or write cycles to the EPP.
These bits are reserved and are always 1.
sec, an EPP time-out event occurs, which aborts the
Enhanced Parallel Port (EPP) Register Set
Parallel Port (Logical Device 4)
115
6.3.2
The DTR register is the SPP Compatible or SPP Extended
data register. A write to DTR sets the state of the eight data
pins on the 25-pin D-shell connector.
6.3.3
This status port is read only. A read presents the current
status of the five pins on the 25-pin D-shell connector, and
the IRQ as shown in Figure 6-5.
The bits of this register have the identical function in EPP
mode as in SPP mode. See Section 6.2.3 for a detailed de-
scription of each bit.
Offset
TABLE 6-5. Enhanced Parallel Port (EPP) Registers
0
1
7
7
00h
01h
02h
03h
04h
05h
06h
07h
FIGURE 6-4. SPP or EPP DTR Register Bitmap
FIGURE 6-5. SPP or EPP STR Register Bitmap
D7
Printer Status
0
1
6
6
SPP or EPP Data Register (DTR), Offset 00h
SPP or EPP Status Register (STR), Offset 01h
D6
ACK Status
0
1
5
5
DATA0
DATA1
DATA2
DATA3
ADDR
Name
DTR
CTR
STR
D5
PE Status
0
1
4
4
D4
SLCT Status
0
1
3
3
D3
ERR Status
0
1
EPP Data Port 0
EPP Data Port 1
EPP Data Port 2
EPP Data Port 3
2
2
Data Bits
EPP Address
SPP Control
Description
SPP Status
D2
IRQ Status
SPP Data
0
1
1
1
D1
Reserved
0
1
0
0
D0
Reset
Required
Reset
Required
Time-Out Status
SPP or EPP Status
SPP or EPP R/W
SPP or EPP
SPP or EPP R/W
SPP or EPP Data
Register (DTR)
Register (STR)
Mode
EPP
EPP
EPP
EPP
EPP
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Offset 00h
Offset 01h
R/W
R/W
R/W
R/W
R/W
R/W
R