PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 208
PC87307VUL
Manufacturer Part Number
PC87307VUL
Description
PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
Manufacturer
National Semiconductor
Datasheet
1.PC87307VUL.pdf
(218 pages)
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13.3.18 Enhanced Parallel Port 1.9 Timing
t
t
t
t
t
t
t
t
t
t
t
t
WW119a
WW19ia
WST19a
WST19ia
WEST19
WPD19h
HRW19
WPDS19
EPDW19
EPD19h
ZWS19a
ZWS19h
DSTRB
ASTRB
ZWS
PD7-0
Symbol
D7-0
IOCHRDY
WAIT
WR
WRITE
RD
or
a. When WAIT is low, t
b. The design guarantees that WRITE will not change from low to high before DSTRB, or ASTRB, goes from low
c. D7-0 is stable 15 nsec before WR becomes active.
t
to high.
WW19a
t
HRW19
WRITE Active from WR Active or WAIT Low
WRITE Inactive from WAIT Low
DSTRB or ASTRB Active from WR or RD Active or WAIT Low
DSTRB or ASTRB Inactive from WR or RD High
DSTRB or ASTRB Active after WRITE Active
PD7-0 Hold after WRITE Inactive
IOCHRDY Active after WR or RD Active or Inactive after WAIT High
PD7-0 Valid after WRITE Active
PD7-0 Valid Width
PD7-0 Hold after DSTRB or ASTRB Inactive
ZWS Valid after WR or RD Active
ZWS Hold after WR or RD Inactive
are measured after WAIT becomes low.
t
{Note a}
t
ZWS19a
t
t
WW19a
WST19a
WEST19
t
{Note a}
WW19a
TABLE 13-54. Enhanced Parallel Port 1.9 Timing Parameters
WST19a
t
WST19a
FIGURE 13-25. Enhanced Parallel Port 1.9 Timing
and t
t
WPDS19
Parameter
WW19a
t
t
WST19ia
ZWS19h
t
HRW19
are measured after WR or RD becomes active; else t
Device Description
t
WW19ia
208
t
WPD19h
t
HRW19
t
ZWS19a
{Note a}
t
WST19a
Notes
t
a b
WST19a
a
c
Min
t
10
80
ZWS19h
0
0
0
Valid
t
Valid
EPDW19
WST19a
Max
t
45
45
65
45
40
15
45
HRW19
t
WST19ia
and
t
EPD19h
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Unit
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