PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 38

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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Bit 7-5 - Parallel Port Mode Select
2.8 UART2 AND INFRARED CONFIGURATION
2.8.1
This read/write register is reset by hardware to 02h.
FIGURE 2-12. SuperI/O UART2 Configuration Register
Bit 0 - TRI-STATE Control for UART signals
Bit 1 - Power Mode Control
0
7
Bit 5 is the LSB.
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled
by bit 4 of the Control2 configuration register of the par-
allel port at offset 02h. See Section 6.5.17 on page 126.
000 - SPP Compatible mode. PD7-0 are always output
001 - SPP Extended mode. PD7-0 direction controlled
010 - EPP 1.7 mode.
011 - EPP 1.9 mode.
100 - IEEE1284 mode (IEEE1284 register set), with no
101 - Reserved.
110 - Reserved.
111 - IEEE1284 mode (IEEE1284 register set), with
This bit controls the TRI-STATE status of UART signals
(except IRQ and DMA signals) when the UART is inac-
tive (disabled). This bit is ORed with a bit of the PMC1
register of the power management device (logical de-
vice 8).
0 - Signals not in TRI-STATE.
1 - Signals in TRI-STATE.
0 - Low power mode.
REGISTER (LOGICAL DEVICE 5)
0
Bank Select Enable
6
This option supports run-time configuration within
the Parallel Port address space. An 8-byte (and
1024-byte) aligned base address is required to ac-
cess these registers. See Chapter 6 on page 111
for details.
signals.
by software.
support for EPP mode.
EPP mode selectable as mode 4.
SuperI/O UART2 Configuration Register,
Index F0h
0
5
0
4
Reserved
0
3
Ring Detection on RI Pin
0
2
Busy Indicator
1
1
Bitmap
Power Mode Control
0
0
Reset
Required
TRI-STATE Control for
UART2 Signals
Configuration Register,
SuperI/O UART2
Index F0h
Configuration
38
Bit 2 - Busy Indicator
Bit 3 - Ring Detection on RI Pin
Bits 6-4 - Reserved
Bit 7 - Bank Select Enable
2.9 UART1 CONFIGURATION REGISTER
2.9.1
This read/write register is reset by hardware to 02h. Its bits
function like the bits in the SuperI/O UART2 Configuration
register.
FIGURE 2-13. SuperI/O UART1 Configuration Register
0
7
1 - Normal power mode.
This read-only bit can be used by power management
software to decide when to power down the logical de-
vice. This bit is also accessed via the PMC3 register of
the power management device (logical device 8).
0 - No transfer in progress.
1 - Transfer in progress.
0 - The UART RI input signal uses the RI pin.
1 - The UART RI input signal is the RING detection
These bits are reserved.
Enables bank switching. If this bit is cleared, all attempts
to access the extended registers are ignored.
(LOGICAL DEVICE 6)
0
Bank Select Enable
6
UART Clock disabled. UART output signals are set
to their default state. The RI input signal can be
programmed to generate an interrupt. Registers
are maintained.
UART clock enabled. The UART is functional when
the logical device is active. This bit is ANDed with a
bit of the PMC3 register of the power management
device (logical device 8)
signal on the RING pin. RING pin is selected by the
APCR2 register of the Advanced Power Control
(APC) module.
SuperI/O UART1 Configuration Register,
Index F0h
0
5
0
4
Reserved
0
3
Ring Detection on RI Pin
0
2
Busy Indicator
1
1
Bitmap
Power Mode Control
0
0
Reset
Required
TRI-STATE Control for
UART1 Pins
Configuration Register,
SuperI/O UART1
Index F0h