LTC485I LINER [Linear Technology], LTC485I Datasheet - Page 8
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LTC485I
Manufacturer Part Number
LTC485I
Description
Low Power RS485 Interface Transceiver
Manufacturer
LINER [Linear Technology]
Datasheet
1.LTC485I.pdf
(12 pages)
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APPLICATIO S I FOR ATIO
The LTC485 output stage will maintain a high impedance
state until the breakdown of the N-channel or P-channel is
reached when going positive or negative respectively. The
output will be clamped to either V
voltage plus a Schottky diode drop, but this voltage is way
beyond the RS485 operating range. This clamp protects
the MOS gates from ESD voltages well over 2000V.
Because the ESD injected current in the N-well or substrate
consists of majority carriers, latchup is prevented by
careful layout techniques.
LTC485
8
RECEIVER
OUTPUTS
OUTPUT
DRIVER
RO
A
B
Figure 11. Receiver t
U U
CC
t
r
, t
or ground by a Zener
W
TTL IN
f
Figure 13. Receiver Propagation Delay Test Circuit
PHL
< 6ns
D
LTC485 • F11
U
100pF
R
100
100pF
Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
the receiver. Using the test circuit of Figure 13, Figures 11
and 12 show the typical LTC485 receiver propagation
delay.
The receiver delay times are:
The driver skew times are:
LTC485 • F13
RECEIVER
BR
OUTPUTS
OUTPUT
DRIVER
Skew = 5ns Typ, V
t
PLH
R
RO
– t
A
B
10ns Max, V
RECEIVER
OUT
PHL
Figure 12. Receiver t
= 9ns Typ, V
CC
CC
= 5V
= 5V, T
CC
PLH
= 5V
A
= – 40 C to 85 C
LTC485 • F12