Z90251 ZILOG [Zilog, Inc.], Z90251 Datasheet - Page 78
Z90251
Manufacturer Part Number
Z90251
Description
eZVision 200 Television Controllers with OSD
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z90251.pdf
(97 pages)
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9.2
PWM1 through PWM11
Two data registers (PWM11H and PWM11L) hold the 14-bit PWM11 ratio. If PWM6
is configured to 14-bit, two data registers (PWM6H and PWM6L) hold the 14-bit
PWM6 ratio. The upper 7 bits control the width of the distributed pulse. The lower
7 bits distribute the minimum resolution pulse in the various time slots. Using this
technique, the pseudo-repetition of frequency is raised up to 128 times faster than
ordinary pulse width modulation.
There are 128 time slots which start from time slot 7Fh to 0h because a 14-bit
binary down counter is used. When the glitch exceeds 127 pulses, the upper 7
bits take precedence and fill 128 pulses of the same width in different locations.
Generating the pulse-train output requires the following equation: Time slot (Fts)
and one cycle of frequency (F14).
When the 6-bit data is 00h, the PWM output is Low. The maximum value is 3Fh
and emits High DC-level output.
A selected PWM cycle/frequency is shown in the following equation:
Bit/
Field
Reserved
P47/
PWM 10
P46/
PWM9
P45/
PWM 8
P44/
PWM 7
Reserved
Fdp (Distribution pulse frequency)=XTAL/128 (Hz)
Fts (Time slot frequency) = XTAL/128 (Hz)
F14 (a cycle/frequency) = XTAL /16384 (Hz)
F6 (a cycle/frequency) = XTAL/16/64 (Hz)
Bit
Position
7, 6
5
4
3
2
1, 0
R/W Value Description
R/W
R/W
R/W
R/W
W
W
R
R
32 KB Television Controller with OSD
0
1
0
1
0
1
0
1
Return 1
No effect
Select PWM 10
Select P47 - POR
Select PWM 9
Select P46 - POR
Select PWM 8
Select P45 - POR
Select PWM 7
Select P44 - POR
Return 1
No effect
PS001301-0800
70
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