AD7492_01 AD [Analog Devices], AD7492_01 Datasheet - Page 15

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AD7492_01

Manufacturer Part Number
AD7492_01
Description
1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC
Manufacturer
AD [Analog Devices]
Datasheet
AD7492 to 80C186 Interface
Figure 23 shows the AD7492 interfaced to the 80C186 micropro-
cessor. The 80C186 DMA controller provides two independent
high-speed DMA channels where data transfer can occur between
memory and I/O spaces. (The AD7492 occupies one of these I/O
spaces.) Each data transfer consumes two bus cycles, one cycle
to fetch data and the other to store data.
After the AD7492 has finished conversion, the BUSY line gen-
erates a DMA request to Channel 1 (DRQ1). As a result of the
interrupt, the processor performs a DMA READ operation
which also resets the interrupt latch. Sufficient priority must
be assigned to the DMA channel to ensure that the DMA
request will be serviced before the completion of the next con-
version. This configuration can be used with 6 MHz and 8 MHz
80C186 processors.
80C186
AD0–AD15
A16–A19
DRQ1
ALE
RD
ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS/DATA BUS
ADDRESS
DECODER
Q
ADDRESS
LATCH
R
S
ADDRESS
BUS
DATA BUS
AD7492
CS
BUSY
RD
DB0–DB9
(DB11)
OPTIONAL
AD7492
CONVST

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