CY7C09289 CYPRESS [Cypress Semiconductor], CY7C09289 Datasheet
CY7C09289
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CY7C09289 Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 16/18 organization (CY7C09279/379) — 64K x 16/18 organization (CY7C09289/389) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100- MHz cycle time • ...
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... TQFP (Top View CY7C09289 (64K x 16) CY7C09279 (32K x 16 equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow- ...
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Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [8] 7 A15L LBL 8 UBL 9 CE0L 10 CE1L 11 CNTRSTL 12 R/WL 13 OEL 14 VCC 15 FT/PIPEL 16 ...
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... Ambient Temperature with Power Applied ..– +125 C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 9. Industrial parts are available in CY7C09289 and Cy7C09389 only Document #: 38-06040 Rev. ** Description –A for 32K, A –A for 64K devices). ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Min –4.0 mA Output LOW Voltage Min +4.0 mA Input HIGH Voltage ...
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AC Test Loads 893 OUTPUT 347 (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 only OUTPUT C V (a) Load 1 ...
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Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...
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Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CH1 CLK R ADDRESS DATA OUT t CKLZ OE Read Cycle ...
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Switching Waveforms (continued) [18, 19] Bank Select Pipelined Read t CYC2 t t CH2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) 0 ...
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Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT Pipelined ...
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Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 DATA ...
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Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT Q x-1 READ EXTERNAL ADDRESS ...
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Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...
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Switching Waveforms (continued) Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST CNTRST t SD DATA ...
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Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS ...
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... Ordering Code [1] 6.5 CY7C09279-6AC 7.5 CY7C09279-7AC 9 CY7C09279-9AC 12 CY7C09279-12AC 64K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09289-6AC 7.5 CY7C09289-7AC 9 CY7C09289-9AC CY7C09289-9AI 12 CY7C09289-12AC 32K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09379-6AC 7.5 CY7C09379-7AC 9 CY7C09379-9AC 12 CY7C09379-12AC 64K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09389-6AC 7.5 CY7C09389-7AC ...
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Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06040 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of ...
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Document Title: CY7C09279/89, CY7C09379/89 32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06040 Issue REV. ECN NO. Date ** 110188 09/29/01 Document #: 38-06040 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00664 ...