W83194BR-903_06 WINBOND [Winbond], W83194BR-903_06 Datasheet
W83194BR-903_06
Related parts for W83194BR-903_06
W83194BR-903_06 Summary of contents
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... W83194BR-903 & W83194BG-903 STEPLESS VIA PT/PM MAIN CLOCK GENERATOR Date: 5/2/2006 Revision: 1.0 ...
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... W83194BR-903 Datasheet Revision History PAGES DATES VERSION 1 n.a. 2 n.a. 09/07/03 0.5 6 10/28/03 0.6 3 7,9,19 12/18/03 0 05/02/06 1 W83194BR-903/W83194BG-903 WEB MAIN CONTENTS VERSION All of the versions before 0.50 are for internal n.a. use. n.a. First published preliminary version. n.a. Modify frequency table n.a. Correction IC version, correction some description and default value 1 ...
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... Register 13: Divisor and Step-less Enable Control (Default: 0Fh) .................................................12 7.15 Register 14: Control (Default: 0Ah)..................................................................................................12 7.16 Register 15: SST & Skew Control (Default: 2Ch) ...........................................................................13 7.17 Register 16: Skew Control (Default: 24h)........................................................................................13 7.18 Register 17: Slew rate Control (Default: 00h)..................................................................................13 7.19 Register 18: Slew rate Control (Default: 00h)..................................................................................14 7.20 Register 19: Slew rate Control (Default: D2h).................................................................................14 W83194BR-903/W83194BG-903 - II - ...
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... Skew Group timing clock .................................................................................................................18 9.4 CPU 0.7V Electrical Characteristics ................................................................................................18 9.5 AGP Electrical Characteristics.........................................................................................................18 9.6 PCI Electrical Characteristics...........................................................................................................19 9.7 24M, 48M Electrical Characteristics ................................................................................................19 9.8 REF Electrical Characteristics .........................................................................................................19 10. ORDERING INFORMATION ......................................................................................................... 20 11. HOW TO READ THE TOP MARKING .......................................................................................... 20 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................. 21 W83194BR-903/W83194BG-903 Publication Release Date: May 2006 - III - Revision 1.0 ...
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... S.S.T. scale to reduce EMI. The W83194BR-903 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-903 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 3 0.7V current-mode Differential pairs clock outputs • ...
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... Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND 4. BLOCK DIAGRAM VTT_PWRGD FS(0:4) & MODE & SEL24_48# PD#* PCI_STOP#* CPU_STOP SCLK* W83194BR-903/W83194BG-903 48 FS1* /REF0 1 47 & FS0 /REF1 2 46 VDDREF 3 45 XIN 4 44 XOUT ...
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... FS2 8 PCI_F1 & FS4 12 PCI0 & MODE W83194BR-903/W83194BG-903 DESCRIPTION Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Bi-directional Pin, Open Drain. Active Low Internal 120kΩ pull-up Internal 120 kΩ pull-down ...
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... I C Control Interface PIN PIN NAME 32 SDATA* 31 SCLK* W83194BR-903/W83194BG-903 TYPE OUT 3.3V PCI free running clock output. OUT 3.3V PCI clock output. Select by pin 12 MODE initial =0. IN Active low, Stop all PCI clock output besides the free running tp120k clocks. Select by pin 12 MODE OUT 3 ...
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... VDDCPU 24 VDD48 34 VDD2.5 48 VDDA 6,11,18,23,28, GND 37,43,47 W83194BR-903/W83194BG-903 TYPE IN Power good input signal is power on trapping with HIGH active. This 3.3V input is level sensitive strobe used to determine FS [4:0]. This pin is HIGH active. IN Power Down Function. This is power down pin, low active tp120k (PD#). Internal 120K pull up OUT Deciding the reference current for the CPUCLK pairs. ...
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... W83194BR-903/W83194BG-903 FS0 CPU (MHZ) 3V66 (MHZ) 0 100.00 1 200.01 0 133.34 0 200.01 1 400.01 0 266.68 0 101.1 1 202.2 0 134.68 0 100.00 1 200.01 0 133.34 0 200.01 1 400.01 0 266.68 0 105.04 1 210.07 0 140 ...
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... Power on latched value of FS2 pin. Default Power on latched value of FS1 pin. Default Power on latched value of FS0 pin. Default: 0 W83194BR-903/W83194BG-903 DESCRIPTION Frequency selection by software via I Enable software program FS [4:0 Select frequency by hardware. 1= Select frequency by software I Enable Spread Spectrum in the frequency table Normal 1 = Spread Spectrum Enabled Enable reload safe frequency when the watchdog is timeout ...
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... Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable Stopped) (Default: BFh) BIT PIN NO PWD 24_48MHz output control Reserved 48MHz output control Reserved REF1 output control REF0 output control 25MHz_1 output control 25MHz_0 output control. W83194BR-903/W83194BG-903 DESCRIPTION DESCRIPTION DESCRIPTION - 8 - ...
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... SAF_FREQ [ SAF_FREQ [0] 0 7.7 Register 6: Reserved (Default: 50h) (Read Only) BIT NAME PWD 7 Reserved 0 6 Reserved 1 5 Reserved 0 4 Reserved 1 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 W83194BR-903/W83194BG-903 DESCRIPTION DESCRIPTION Reserved Reserved Reserved Reserved - 9 - Publication Release Date: May 2006 Revision 1.0 ...
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... Register 7: Winbond Chip ID (Default: 70h) (Read Only) BIT NAME PWD 7 CHPI_ID [7] 0 Winbond Chip ID. W83194BR-903 (SA5870) 6 CHPI_ID [6] 1 Winbond Chip ID. 5 CHPI_ID [5] 1 Winbond Chip ID. 4 CHPI_ID [4] 1 Winbond Chip ID. 3 CHPI_ID [3] 0 Winbond Chip ID. 2 CHPI_ID [2] 0 Winbond Chip ID. ...
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... Reserved 1 Reserved 6 DS9 1 Define the AGP divider ratio Table-2 integrate the all divider configuration 5 DS5 1 4 Reserved 1 Reserved 3 Reserved 1 2 DS2 0 Define the CPU divider ratio Refer to Table-2 1 DS1 1 0 DS0 1 W83194BR-903/W83194BG-903 DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 2006 - 11 - Revision 1.0 ...
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... SPCNT [ SPCNT [ SPCNT [ SPCNT [ SPCNT [0] 0 W83194BR-903/W83194BG-903 AGP Bit5 1 00 Div7 Div2 Div12 Div8 DESCRIPTION 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS< ...
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... PCI_F1 / PCI_F0 slew rate control 11: Strong, 00: Weak, 10/01: Normal 4 PCI_F0_S1 0 3 AGP_2_S2 0 AGP2 slew rate control 11: Strong, 00: Weak, 10/01: Normal 2 AGP_2_S1 0 1 AGP_10_S2 0 AGP_1 /AGP_0 slew rate control 11: Strong, 00: Weak, 10/01: Normal 0 AGP_10_S1 0 W83194BR-903/W83194BG-903 DESCRIPTION 00: Down 1% 01: Down 0.5% 10: Center +/- 0.5% 11: Center +/- 0.25% DESCRIPTION DESCRIPTION - 13 - Publication Release Date: May 2006 Revision 1.0 ...
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... WD_TIME [ WD_TIME [ WD_TIME [0] 0 W83194BR-903/W83194BG-903 DESCRIPTION DESCRIPTION Stop CPU1 clocks, 1: Enable stop feature, 0: Disable Stop CPU0 clocks, 1: Enable stop feature, 0: Disable 25MHz_1,0 slew rate control 11: Strong, 00: Weak, 10/01: Normal Invert the 48MHz phase phase with 24_48MHz 1: 180 degrees out of phase ...
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... Output frequency according to FIX frequency Reg21 bit 0~2 3 SRCF0 0 SRC frequency select 2 ASEL_2 0 Asynchronous AGP/PCI frequency table selection ASEL_<2:0> 1 ASEL_1 0 0 ASEL_0 0 W83194BR-903/W83194BG-903 DESCRIPTION 001 33M 010: 75.43 / 37.7M 011 44M 100 44M 101 33M 110: 75.43 / 33M 111 33M 000: Clock from PLL1 - 15 - Publication Release Date: May 2006 Revision 1.0 ...
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... ACCESS INTERFACE The W83194BR-903 provides I W83194BR-903 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8 ...
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... Input ESD protection (Human body model) 9.2 General Operating Characteristics VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI= 3.3V PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance W83194BR-903/W83194BG-903 ± SYMBOL MIN MAX UNITS ...
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... Cycle to Cycle jitter Duty Cycle 9.5 AGP Electrical Characteristics ± VDDAGP= 3. PARAMETER Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-903/W83194BG-903 ± MIN TYP MAX UNITS 1.5 2.6 3.5 ns 200 ps 250 ps 500 ...
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... REF Electrical Characteristics ± VDDREF= 3. PARAMETER Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-903/W83194BG-903 ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 500 2000 ps 500 2000 ...
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... W83194BG-903 28051234 342GAASA 1st line: Winbond logo and the type number: Normal:W83194BR-903, Lead free part:W83194BG-903 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 320: packages made in '2003, week 42 G: assembly house ID ...
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... PACKAGE DRAWING AND DIMENSIONS W83194BR-903/W83194BG-903 Publication Release Date: May 2006 - 21 - Revision 1.0 ...
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... FAX: 886-2-8751-3579 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. W83194BR-903/W83194BG-903 Important Notice Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U ...