MAXQ7665AATM+ MAXIM [Maxim Integrated Products], MAXQ7665AATM+ Datasheet - Page 24

• Manufacturer Part Number: MAXQ7665AATM+
• Description: 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems
• Manufacturer: MAXIM [Maxim Integrated Products]

As illustrated in Figure 7, the high-frequency internal
RC oscillator (HFRCCLK) drives the watchdog timer
through a series of dividers. The divider output is pro-
grammable and determines the timeout interval. When
enabled, the interrupt flag WDIF is set when a timeout
is reached. A system reset then occurs after a time
delay (based on the divider ratio).
The watchdog timer functions as the source of both the
watchdog interrupt and the watchdog reset. The inter-
rupt timeout has a default divide ratio of 2
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Figure 7. Watchdog Functional Diagram
Figure 8. Type 2 Timer Functional Diagram
24
HFRCCLK
(7.6MHz)
_______________________________________________________________________________________
WD1
WD0
RWT
T2CLK
DIV 2
12
2
12
C/T2
2
15
TIME
DIV 2
2
TIMEOUT
18
RESET
WDIF
TR2L
3
2
21
DETECTION AND
T2POL[0]
EWDI
CCF[1:0]
GATING
EWT
EDGE
G2EN
SS2
TR2
DIV 2
3
T2MD
12
of the HFR-
DIV 2
TIMER EVENT
3
INTERRUPT
WTRF
RESET
T2CL
T2RL
T2L
CCLK, with the watchdog reset set to timeout 2
cycles later. With the nominal RC oscillator value of
7.6MHz, an interrupt timeout occurs every 539µs, fol-
lowed by a watchdog reset 67.4µs later. The watchdog
timer is reset to the default divide ratio following any
reset. Using the WD0 and WD1 bits in the WDCN regis-
ter, other divide ratios can be selected for longer
watchdog interrupt periods. If the WD[1:0] bits are
changed before the watchdog interrupt timeout occurs
(i.e. before the watchdog reset counter begins), the
watchdog timer count is reset. All watchdog timer reset
timeouts follow the programmed interrupt timeout 512
source clock cycles later. For more information on the
MAXQ7665A–MAXQ7665D watchdog timer, refer to the
MAXQ7665/MAXQ7666 User’s Guide.
The MAXQ7665A–MAXQ7665D include three 16-bit
timer channels. Each timer is a type 2 timer implement-
ed in the MAXQ family (see Figure 8). Two of the timers
are accessible through I/Os, and one is accessible only
through software. Type 2 timers are auto-reload 16-bit
timers/counters offering the following functions:
• 8-bit/16-bit timer/counter
• Up/down auto-reload
• Counter function of external pulse
• Capture
• Compare
T2CH
T2RH
T2H
T2L COMPARE MATCH
T2H:T2L COMPARE MATCH OR
T2H COMPARE MATCH
T2L OVERFLOW
T2H:T2L OVERFLOW OR
T2H OVERFLOW
Timer and PWM
9
clock