MAX5318 MAXIM [Maxim Integrated Products], MAX5318 Datasheet - Page 29

• Manufacturer Part Number: MAX5318
• Description: 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface
• Manufacturer: MAXIM [Maxim Integrated Products]

The SPI interface supports speeds up to 50MHz. When
CS is high, the remaining interface inputs are disabled to
reduce transient currents. The interface supports daisy
chaining to enable multiple devices to be controlled on
the same SPI bus.
The device has a double-buffered interface consisting
of two register banks: the input register and the DAC
register. The input register for DIN/GAIN/OFFSET is con-
nected directly to the 24-bit SPI input shift register. The
DAC latch contains the DAC code after digital process-
ing and is loaded as defined in the LDAC and BUSY
Interaction section above.
A valid SPI frame is 24-bit wide with 4-bit command R3
to R0, 18-bit data D17 to D0, and 2 unused LSBs. A full
24-bit SPI command sequence is required for all SPI
command operations, regardless of the number of data
bits actually used for the command. Any commands
terminating with less than a full 24-bit sequence will be
aborted without impacting the operation of the part (sub-
ject to t
the SPI input register or DAC and it continues to hold the
preceding valid data. If a command sequence with more
than 24 bits is provided, the command will be executed
on the 24th SCLK falling edge and the remainder of the
command will be ignored.
All SPI commands result in the device assuming con-
trol of the DOUT line from the first SCLK edge through
the 24th SCLK edge. After relinquishing the DOUT line,
the MAX5318 returns to a high-impedance mode. An
optional bus hold circuit can be engaged to hold DOUT
at its last bit value while not interfering with other devices
on the bus.
DOUT is disabled at power-up and must be enabled
through the SPI interface. When enabled, DOUT echoes
the 4-bit command plus 18-bit data, which is being
programmed. During readback, DOUT echoes the 4-bit
command followed by the true readback data depending
Table 9. SPI Command and Data Mapping with Clock Falling Edges
Note that ‘X’ is don’t care.
Maxim Integrated
CLOCK
EDGE
DIN
DOUT
CSA
18-Bit, High-Accuracy Voltage Output DAC with
R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9
1
0 R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9
timing requirements). Data is not written into
Digital Gain, Offset Control, and SPI Interface
2
3
4
5
6
7
Serial Interface
8
9
Overview
10
11
12
upon the type of read command.
positions for DOUT and DIN within the 24-bit SPI frame.
The device is designed such that SCLK idles low, and
DIN and DOUT change on the rising clock edge and get
latched on the falling clock edge. The SPI host controller
should be set accordingly.
The READY pulse appears 24 clock cycles after the neg-
ative edge of CS as shown in
be used as the CS line for the next device in the daisy
chain. Since the device looks at the first 24 bits of the
transmission following the falling edge of CS, it is pos-
sible to daisy-chain the device with different command
word lengths. READY goes high after CS is driven high.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
the device. As the data propagates through the daisy
chain, each individual command in the chain is executed
on the 24th falling clock edge following the falling edge
of the respective CS input. To update just one device
in a daisy chain, send the no-op command to the other
device in the chain. To update the first device in the
chain, raise the CS input after writing to that device.
Because daisy-chain operation requires parallel-
ing the DOUTs of all the MAX5318 in the chain, the
NO_HOLDEN bit in register 0x4 or 0xC should be set
to 1 for all devices. Doing so ensures that DOUT goes
into high-impedance after the SPI frame is complete
(i.e. after the 24th clock cycle) as shown in
The diagram in
tion of the MAX5318 in a typical SPI application. If more
than one peripheral device shares the DOUT bus, the
NO_HOLDEN bit in register 0x4 or 0xC should be set to 1
for the MAX5318. Doing so ensures that DOUT goes into
high-impedance after the SPI frame is complete (i.e. after
the 24th clock cycle).
13
Daisy-Chain SPI Operation Using READY Output
D8
14
D7
D8
15
D6
D7
16
Figure 9
D5
D6
17
D4
D5
18
shows a stand-alone connec-
D3
D4
19
Figure 7
Stand-Alone Operation
D2
D3
20
Table 9
MAX5318
and can therefore
D1
D2
21
shows the bit
D0
D1
22
Figure
D0
23
X
24
X
X
8.
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