DAC7528UB BURR-BROWN [Burr-Brown Corporation], DAC7528UB Datasheet - Page 4

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DAC7528UB

Manufacturer Part Number
DAC7528UB
Description
CMOS Dual 8-Bit Buffered Multiplying DIGITAL-TO-ANALOG CONVERTER
Manufacturer
BURR-BROWN [Burr-Brown Corporation]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DAC7528UB
Manufacturer:
BB/TI
Quantity:
732
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
TYPICAL PERFORMANCE CURVES
At V
ABSOLUTE MAXIMUM RATINGS
NOTES:
specified for device in socket for PDIP package.
CAUTION: (1) Do not apply voltages higher than V
potential on any terminal except V
3 and 19). (2) The digital control inputs are zener-protected: however,
permanent damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam at all times until ready
to use. (3) Use proper antistatic handling procedures. (4) Absolute
Maximum Ratings apply to both packaged devices and DICE. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.
V
V
R
Digital Input Voltage Range ................................................ –0.3V to V
Output Voltage (pins 2, 20) ................................................ –0.3V to V
Operating Temperature Range U,P ................................ –40 C to +85 C
Junction Temperature .................................................................. +150 C
Storage Temperature ..................................................... –60 C to +150 C
Lead Temperature (soldering, 10s) ............................................. +300 C
DD
REFA, B
FA,B
DD
JA
JC
7.0
6.0
5.0
4.0
3.0
2.0
1.0
to GND ................................................................................. 0V, +7V
= +5V; V
0
to GND ................................................................................... 25V
U package ........................................................................ 105 C/W
P package ........................................................................... 85 C/W
P package .......................................................................... 35 C/W
U package ......................................................................... 60 C/W
0
to GND ................................................................................ 25V
JA
ELECTROSTATIC
DISCHARGE SENSITIVITY
is specified for worst case mounting conditions, i.e.,
SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE
REFA,B
®
DAC7528
= +10V; I
1.0
OUT
DICE ............................... 0 C to +70 C
= GND = 0V: T = Full Temperature Range Specification under Absolute Maximum Ratings unless otherwise noted.
REFA, B
V
IN
2.0
(V)
V
(pins 4 and 18) and R
DD
= +5V
3.0
DD
or less than GND
FBA, B
4.0
(pins
JA
DD
DD
is
4
WRITE CYCLE TIMING DIAGRAM
Digital Inputs: All digital inputs of the DAC7528 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500 )
applied to each digital input.
Analog Pins: Each analog pin has been tested to Burr-
Brown's analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500 ) ap-
plied to each pin. R
some sensitivity.
MODE SELECTION TABLE
DAC A/DAC B
DAC A/DAC B
L
H
X
X
NOTE: All input signal rise and fall times are measured from 10% to 90%
of V
measurement reference level is (V
–1
–2
–3
–4
–5
5
4
3
2
1
0
(DB0-DB7)
–40
DD
Data In
. V
WR
DD
CS
–20
= +5V, t
0
r
CS
= t
H
X
L
L
FB A
DAC7528 GAIN TC
f
Temperature (°C)
= 20ns; V
20
, V
REF A
IH
t
t
AS
CS
V
V
+ V
WR
40
DD
IH
IL
t
X
H
L
L
WR
, R
IL
t
In Stable
= +15V, t
DS
)/2.
Data
FB B
60
, and V
DAC A
WRITE
t
HOLD
HOLD
HOLD
DH
r
t
t
= t
CH
AH
80
f
= 40ns. Timing
REF B
100
DAC B
WRITE
HOLD
HOLD
HOLD
show
V
0
V
0
V
0
V
0
DD
DD
DD
DD

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