MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 281

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

RTS1/L1RQ/GCIDCL—Request to Send/Layer-1 Request/GCI Clock Out
BRG1—Baud Rate Generator 1
5.14 NMSI2 PORT OR PORT A PINS
The NMSI2 port or port A pins are shown in Figure 5-11.
These eight pins can be used either as the NMSI2 port or as a general-purpose parallel I/O
port. Each one of these pins can be configured individually to be general-purpose I/O pins
or a dedicated function in NMSI2. When they are used as NMSI2 pins, they function exactly
as the NMSI1 pins in NMSI mode.
The PA7 signal in dedicated mode becomes serial data strobe 2 (SDS2) in IDL and GCI
modes. In IDL/GCI modes, the SDS2–SDS1 outputs may be used to route the B1 and/or B2
channels to devices that do not support the IDL or GCI buses. This is configured in the SI-
MODE and SIMASK registers. If SCC2 is in NMSI mode, this pin operates as BRG2, the out-
put of the SCC2 baud rate generator, unless SDS2 is enabled to be asserted during the B1
or B2 channels of ISDN (bits SDC2–SDC1 of SIMODE). SDS2/BRG2 may be temporarily
disabled by configuring it as a general-purpose output pin. The input buffers have Schmitt
MOTOROLA
If SCC1 is programmed not to support CTS1 (in the SCC1 mode register), then this pin
may be used as an external interrupt source. The current value of the CTS1 pin may be
read in the SCCS1 register. See 4.5.8.3 SCC Status Register (SCCs) for details.
This output is the NMSI1 RTS signal in NMSI mode, the IDL request signal in IDL mode,
or the GCI data clock output in GCI mode.
RTS1 is asserted when SCC1 (in NMSI mode) has data or pad (flags or syncs) to transmit.
In GCI mode this pin is used to output the GCI data clock.
This output is always the baud rate generator clock of SCC1. (This pin used to be NC2.)
The BRG clock output on the BRG pins is 180 degrees out of phase with the internal BRG
clock output on the RCLK and TCLK pins. This statement applies to all BRG pins: BRG1,
BRG2, and BRG3. The BRG1 output can be disabled by setting bit 11 in the CKCR reg-
ister (see 3.9 Clock Control Register). When BRG1 is disabled the pin is driven high.
Figure 5-11. NMSI2 Port or Port A Pins
MC68302
MC68302 USER’S MANUAL
RXD2 / PA0
TXD2 / PA1
TCLK2 / PA3
CTS2 / PA4
CD2 / PA6
BRG2 / SDS2 / PA7
RCLK2 / PA2
RTS2 / PA5
Signal Description
5-17