MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 381

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68302 Applications
D.6.1 M68000 Core
The M68000 core processor on the MC68302 is instruction and timing compatible with the
standard MC68000 (16-bit) or MC68008 (8-bit) versions of the M68000 Family. The core
supports bus lock during read-modify-write cycles, a low latency interrupt mechanism, and
bus width configuration. It does not support the older M6800 peripherals.
D.6.2 Communications Processor
The communication processor consists of a RISC processor, three serial communication
controllers (SCCs), six DMA channels for the three SCCs, a programmable physical inter-
face, a programmable serial communication port (SCP), and two serial management con-
trollers (SMCs). The RISC processor, a separate processor from the M68000 core
processor, is dedicated to the service of the SCCs, SCP, and SMCs.
The MC68302 supports three, full-duplex, independent SCCs, which support HDLC, UART,
BISYNC, DDCMP, and V.110 protocols as well as transparent mode.
The physical interface supports a standard nonmultiplexed interface for each of the three
SCCs (TXD, RXD, TCLK, RCLK, CTS, RTS, and CD) as well as several multiplexed
modes.In multiplexed modes, up to three SCCs can be time-multiplexed onto the same se-
rial channel. The multiplexed modes include IDL, GCI, and PCM highway.
The SCP is a full-duplex, synchronous, character-oriented channel that provides a three-
wire interface. It is used to control and program SPI-type devices. The SCP implements a
subset of Motorola's SPI interface.
The two SMCs are used to exchange control information multiplexed with the 2B + D data
in the IDL or GCI buses.
D.6.3 System Integration Block
The system integration block incorporates general-purpose peripherals that eliminate the
glue logic found in most M68000 systems. It includes an independent DMA controller (ID-
MA), an interrupt controller, parallel l/O ports, 1152-byte dual-port RAM, two timers, one
watchdog timer, chip-select lines and wait-state generation logic, a bus arbiter, low power
modes, core disable logic, on-chip clock generator, and a hardware watchdog.
D.6.4 IDL Bus
The IDL was developed to maximize the portability of the various chips required in an ISDN
system. It provides a consistent interface definition across which a family of ISDN chips will
be able to transport data (see Figure D-12).
MOTOROLA
MC68302 USER’S MANUAL
D-31