MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 7

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

3.5.3.1
3.5.3.2
3.5.3.3
3.6
3.6.1
3.6.2
3.6.2.1
3.6.2.2
3.6.3
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.5.1
3.8.5.2
3.8.6
3.8.7
3.8.7.1
3.8.7.2
3.8.7.2.1
3.8.7.2.2
3.8.7.2.3
3.9
3.9.1
3.10
3.10.1
3.10.2
3.10.3
3.10.4
3.10.5
3.10.6
4.1
4.2
4.3
4.3.1
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Paragraph
Number
MOTOROLA
Software Watchdog Timer Operation .................................................... 3-41
Software Watchdog Reference Register (WRR) ................................... 3-41
Software Watchdog Counter (WCN) ..................................................... 3-42
External Chip-Select Signals and Wait-State Logic .............................. 3-42
Chip-Select Logic Key Features............................................................ 3-45
Chip-Select Registers............................................................................ 3-45
Base Register (BR3–BR0) .................................................................... 3-45
Option Registers (OR3–OR0) ............................................................... 3-47
Chip Select Example ............................................................................. 3-48
On-Chip Clock Generator...................................................................... 3-49
System Control...................................................................................... 3-50
System Control Register (SCR) ............................................................ 3-50
System Status Bits ................................................................................ 3-51
System Control Bits............................................................................... 3-52
Disable CPU Logic (M68000)................................................................ 3-54
Bus Arbitration Logic ............................................................................. 3-56
Internal Bus Arbitration.......................................................................... 3-56
External Bus Arbitration......................................................................... 3-58
Hardware Watchdog.............................................................................. 3-59
Reducing Power Consumption.............................................................. 3-60
Power-Saving Tips ................................................................................ 3-60
Low-Power (Standby) Modes ................................................................ 3-60
Low-Power Mode .................................................................................. 3-61
Lowest Power Mode.............................................................................. 3-62
Lowest Power Mode with External Clock .............................................. 3-62
Clock Control Register .......................................................................... 3-64
Freeze Control....................................................................................... 3-65
Dynamic Ram Refresh Controller.......................................................... 3-66
Hardware Setup .................................................................................... 3-66
DRAM Refresh Controller Bus Timing................................................... 3-67
Refresh Request Calculations............................................................... 3-67
Initialization............................................................................................ 3-68
DRAM Refresh Memory Map ................................................................ 3-68
Programming Example.......................................................................... 3-69
Main Controller ........................................................................................ 4-1
SDMA Channels...................................................................................... 4-3
Command Set ......................................................................................... 4-5
Command Execution Latency ................................................................. 4-7
Serial Channels Physical Interface.......................................................... 4-7
IDL Interface.......................................................................................... 4-11
GCI Interface ......................................................................................... 4-14
PCM Highway Mode.............................................................................. 4-16
Nonmultiplexed Serial Interface (NMSI) ................................................ 4-19
Communications Processor (CP)
MC68302 USER’S MANUAL
Section 4
Title
Table of Contents
Number
Page
vii