CY8C38_1105 CYPRESS [Cypress Semiconductor], CY8C38_1105 Datasheet - Page 70
CY8C38_1105
Manufacturer Part Number
CY8C38_1105
Description
Programmable System-on-Chip (PSoC) Multiply and divide instructions
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C38_1105.pdf
(130 pages)
- Current page: 70 of 130
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Table 11-3. AC Specifications
Document Number: 001-11729 Rev. *S
Note
F
F
Svdd
T
T
T
T
24. Based on device characterization (Not production tested).
STARTUP
SLEEP
IO_INIT
CPU
BUSCLK
HIBERNATE
Parameter
CPU frequency
Bus frequency
V
Time from V
≥ IPOR to I/O ports set to their reset
states
Time from V
≥ PRES to CPU executing code at
reset vector
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
DD
ramp rate
Description
DDD
DDD
[24]
/V
/V
DDA
DDA
/V
/V
1.71 V
5.5 V
3.3 V
0.5 V
CCD
CCD
0 V
DC
/V
/V
CCA
CCA
Figure 11-4. F
Valid Operating Region with SMP
1.71 V ≤ V
1.71 V ≤ V
V
V
boot mode (48 MHz typ.)
V
V
IMO boot mode (12 MHz typ.)
CCA
DDA
CCA
DDA
Valid Operating Region
/V
/V
/V
/V
CPU Frequency
DDA
DDD
CCD
DDD
1 MHz
DDD
DDD
Conditions
, no PLL used, fast IMO
, no PLL used, slow
= regulated from
= regulated from
CPU
≤ 5.5 V
≤ 5.5 V
vs. V
DD
10 MHz
67 MHz
PSoC
Min
DC
DC
–
–
–
–
–
–
®
3: CY8C38 Family
Typ
–
–
–
–
–
–
–
–
Data Sheet
67.01
67.01
Max
100
10
33
66
15
Page 70 of 130
1
Units
MHz
MHz
V/ns
µs
µs
µs
µs
µs
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