MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 264
MC68HC08AZ60ACFU
Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC08AZ60ACFU.pdf
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Serial Peripheral Interface (SPI)
Advance Information
264
NOTE:
NOTE:
NOTE:
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic ‘0’. A mode fault in a master
SPI causes the following events to occur:
To prevent bus contention with another master SPI after a mode fault
error, clear all data direction register (DDR) bits associated with the SPI
shared port pins.
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit.
Reading SPMSTR when MODF = 1 will indicate a MODE fault error
occurred in either master mode or slave mode.
When configured as a slave (SPMSTR = ‘0’), the MODF flag is set if SS
goes high during a transmission. When CPHA = ‘0’, a transmission
begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA
= ‘1’, the transmission begins when the SPSCK leaves its idle level and
SS is already low. The transmission continues until the SPSCK returns
to its IDLE level following the shift of the last data bit. See Transmission
Formats.
When CPHA = ‘0’, a MODF occurs if a slave is selected (SS is at logic
‘0’) and later deselected (SS is at logic ‘1’) even if no SPSCK is sent to
that slave. This happens because SS at logic ‘0’ indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = ‘0’.
When CPHA = ‘1’, a slave can be selected and then later deselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = ‘0’), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
•
•
•
•
•
If ERRIE = ‘1’, the SPI generates an SPI receiver/error CPU
interrupt request.
The SPE bit is cleared.
The SPTE bit is set.
The SPI state counter is cleared.
The data direction register of the shared I/O port regains control of
port drivers.
Serial Peripheral Interface (SPI)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
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