PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 136
PIC18C242
Manufacturer Part Number
PIC18C242
Description
High-Performance Microcontrollers with 10-Bit A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C242.pdf
(296 pages)
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PIC18CXX2
14.3.5
In I
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 14-14: BAUD RATE GENERATOR BLOCK DIAGRAM
FIGURE 14-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DS39026B-page 136
2
C master mode, the reload value for the BRG is
BAUD RATE GENERATOR
SDA
SCL
BRG
value
BRG
reload
SSPM3:SSPM0
03h
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SSPM3:SSPM0
SCL is sampled high, reload takes
place and BRG starts its count.
Control
Reload
01h
CLKOUT
Preliminary
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
Reload
DX-1
remented twice per instruction cycle (T
and Q4 clocks. In I
reloaded automatically. If Clock Arbitration is taking
place for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
BRG Down Counter
SSPADD<6:0>
SCL allowed to transition high
03h
2
C master mode, the BRG is
Fosc/4
02h
7/99 Microchip Technology Inc.
CY
) on the Q2
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