PIC18F2450 MICROCHIP [Microchip Technology], PIC18F2450 Datasheet - Page 208

• Manufacturer Part Number: PIC18F2450
• Description: 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2450/4450
18.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 18-5:
TABLE 18-3:
DS39760A-page 206
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
File Name
Program Verification and
Code Protection
®
devices.
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
(PIC18F2450/4450)
Unimplemented
Unimplemented
Unimplemented
Boot Block
16 Kbytes
Read ‘0’s
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Bit 7
—
—
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
Advance Information
000000h
0007FFh
000FFFh
001000h
001FFFh
002000h
003FFFh
1FFFFFh
Address
WRTC
Range
Bit 5
—
—
—
—
—
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
Bit 4
—
—
—
—
—
—
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Bit 3
—
—
—
—
—
—
Controlled By:
Bit 2
© 2006 Microchip Technology Inc.
—
—
—
—
—
—
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—