PIC18F2450 MICROCHIP [Microchip Technology], PIC18F2450 Datasheet - Page 239
PIC18F2450
Manufacturer Part Number
PIC18F2450
Description
28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2450.pdf
(320 pages)
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MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
W
Q1
=
1
literal ‘k’
Move Literal to W
MOVLW k
0
k
None
The eight-bit literal ‘k’ is loaded into W.
1
MOVLW
Read
0000
Q2
5Ah
k
W
255
1110
5Ah
Process
Data
Q3
kkkk
Write to W
Advance Information
Q4
kkkk
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
PIC18F2450/4450
Q1
=
=
=
=
register ‘f’
Move W to f
MOVWF
0
a
(W)
None
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
MOVWF
Read
0110
Q2
4Fh
FFh
4Fh
4Fh
f
[0,1]
255
f
REG, 0
f {,a}
111a
Process
Data
Q3
DS39760A-page 237
95 (5Fh). See
ffff
register ‘f’
Write
Q4
ffff
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