AT83C24B-TIRIL ATMEL [ATMEL Corporation], AT83C24B-TIRIL Datasheet - Page 16
AT83C24B-TIRIL
Manufacturer Part Number
AT83C24B-TIRIL
Description
Smart Card Reader Interface with Power Management
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT83C24B-TIRIL.pdf
(42 pages)
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Warm reset
16
AT83C24
ISO 7816 constraints: ta = 200 card clock cycles
Note:
The AT83C24 offers a simple and accurate way to control the CRST signal during a warm reset.
After an activation sequence (cold reset), a warm reset is started with a low level on CRST dur-
ing a define delay (between 40000 and 45000 clock cycles for example).
The ART bit, the TIMER 1 and the TIMER 0 registers are used to control CRST.
The first step is to load the number of CCLK cycles with CRST=0 in TIMER registers.
The warm reset is started by setting ART bit (if ART bit is already set, reset ART before).
The CRST signal will be equal to 0 during the number of clock cycles programmed in TIMER 1
and TIMER 0. Then, the CRST signal will be at 1.
Figure 12. Warm reset with ART bit = 1
Timer[1-0] reset value is 400.
CRST
CCLK
CVCC
CIO
400 card clock cycles< = tb
400 card clock cycles< = tc < = 40000 card clock cycles
ART = 1
t
t = TIMER value
4234G–SCR–01/07
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