PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 139

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 10-5:
 2011 Microchip Technology Inc.
RB0/AN12/
INT0/RP3
RB1/AN10/
PMBE/RTCC/
RP4
RB2/AN8/
CTED1/PMA3/
REFO/RP5
RB3/AN9/
CTED2/PMA2/
RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in ANCON1 first.
All other pin functions are disabled when ICSP™ or ICD are enabled.
This bit is not available on 28-pin devices.
PORTB I/O SUMMARY
Function
PMBE
PMA3
PMA2
CTED1
CTED2
RTCC
REFO
AN12
AN10
INT0
RB0
RP3
RB1
RP4
RB2
AN8
RP5
RB3
AN9
RP6
(3)
(3)
(3)
Setting
TRIS
1
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
PORTB<0> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<0> data output; not affected by analog input.
A/D input channel 12.
External interrupt 0 input.
Remappable peripheral pin 3 input.
Remappable peripheral pin 3 output.
PORTB<1> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<1> data output; not affected by analog input.
A/D input channel 10.
Parallel Master Port byte enable output.
Real Time Clock Calendar output.
Remappable peripheral pin 4 input.
Remappable peripheral pin 4 output.
PORTB<2> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<2> data output; not affected by analog input.
A/D input channel 8.
CTMU Edge 1 input.
Parallel Master Port address.
Reference output clock.
Remappable peripheral pin 5 input.
Remappable peripheral pin 5 output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
A/D input channel 9.
CTMU edge 2 input.
Parallel Master Port address.
Remappable peripheral pin 6 input.
Remappable peripheral pin 6 output.
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Description
DS39932D-page 139
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